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TDA4VH-Q1: Configure sgmii&serdes

Part Number: TDA4VH-Q1

Hi team,

In the sdk8.6 platform, the sgmii phy of 2-0 is debugged in rtos, which requires configuration of sgmii and serdes:

serdes1 lane 1

serdes 2 lane 0 1 2 3 4 

But PLL errors occur during the process:

CpswMacPort_setSgmiiInterface: MAC 4: SERDES PLL is not locked

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[MCU2_0] 17.794998 s: EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0] 17.810964 s: PHY 0 is no alive
[MCU2_0] 17.811022 s: PHY 1 is no alive
[MCU2_0] 17.811053 s: PHY 2 is alive
[MCU2_0] 17.811080 s: PHY 3 is no alive
[MCU2_0] 17.811107 s: PHY 4 is no alive
[MCU2_0] 17.811135 s: PHY 5 is no alive
[MCU2_0] 17.811161 s: PHY 6 is no alive
[MCU2_0] 17.811187 s: PHY 7 is no alive
[MCU2_0] 17.811214 s: PHY 8 is no alive
[MCU2_0] 17.811241 s: PHY 9 is no alive
[MCU2_0] 17.811267 s: PHY 10 is no alive
[MCU2_0] 17.811295 s: PHY 11 is no alive
[MCU2_0] 17.811323 s: PHY 12 is no alive
[MCU2_0] 17.811350 s: PHY 13 is no alive
[MCU2_0] 17.811377 s: PHY 14 is no alive
[MCU2_0] 17.811404 s: PHY 15 is no alive
[MCU2_0] 17.811432 s: PHY 16 is no alive
[MCU2_0] 17.811459 s: PHY 17 is no alive
[MCU2_0] 17.811486 s: PHY 18 is no alive
[MCU2_0] 17.811513 s: PHY 19 is no alive
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

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{
/* Configure SerDes clocks */
EthFwBoard_configTorrentClks();
/* Configure SerDes for QSGMII functionality */
boardStatus = Board_serdesCfgSgmii();
EnetAppUtils_assert(boardStatus == BOARD_SOK);
boardStatus = Board_serdesCfgSgmii_serdes1();
// EnetAppUtils_assert(boardStatus == BOARD_SOK);
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

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Board_STATUS Board_CfgSgmii_serdes1(void)
{
CSL_SerdesResult result;
CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
CSL_SerdesLaneEnableParams serdesLane0EnableParams = {0};
printf("%s %d \n",__func__,__LINE__);
memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));
/* SGMII Config */
serdesLane0EnableParams.serdesInstance = (CSL_SerdesInstance)CSL_TORRENT_SERDES1;
serdesLane0EnableParams.baseAddr = CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE;
serdesLane0EnableParams.refClock = CSL_SERDES_REF_CLOCK_100M;
serdesLane0EnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT1;
serdesLane0EnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;
serdesLane0EnableParams.numLanes = 0x2;
serdesLane0EnableParams.laneMask = 0x4;
serdesLane0EnableParams.SSC_mode = CSL_SERDES_NO_SSC;
serdesLane0EnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;
serdesLane0EnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
serdesLane0EnableParams.phyInstanceNum = BOARD_SERDES_LANE_SELECT_CPSW;
serdesLane0EnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

According to the print, it seems like the 2-0 is stuck.

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Board_ethConfigCpsw9g 663
[MCU2_0] 61.678121 s: Board_CfgSgmii_serdes1 393
[MCU2_1] 47.263577 s: CIO: Init ... Done !!!
[MCU2_1] 47.263628 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1] 47.263661 s: CPU is running FreeRTOS
[MCU2_1] 47.263681 s: APP: Init ... !!!
[MCU2_1] 47.263700 s: SCICLIENT: Init ... !!!
[MCU2_1] 47.263865 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_1] 47.263899 s: SCICLIENT: DMSC FW revision 0x8
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

The customer would like to know how to configure the sgmii and serdes needed in the schematic and make sure they are working? Thanks.

Best Regards,

Cherry

  • Hi,

    Giving some updates as follows:

    For serdes 1 tx1/rx1 (lane1), the customer made the following modifications and did not get stuck. But it says PLL is not locked: 

    ti-processor-sdk-rtos-j784s4-evm-08_06_00_14\ethfw\utils\board\src\j784s4\board_j784s4_evm.c

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    if (gEthFwBoard.serdesAllowed)
    {
    + Sciclient_pmSetModuleState(TISCI_DEV_SERDES_10G1,
    + TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
    + TISCI_MSG_FLAG_AOP,
    + SCICLIENT_SERVICE_WAIT_FOREVER);
    /* Configure SerDes clocks */
    - // EthFwBoard_configTorrentClks();
    +EthFwBoard_configTorrentClks1();
    /* Configure SerDes for QSGMII functionality */
    // boardStatus = Board_serdesCfgSgmii();
    // EnetAppUtils_assert(boardStatus == BOARD_SOK);
    + boardStatus = Board_serdesCfgSgmii_serdes1();
    EnetAppUtils_assert(boardStatus == BOARD_SOK);
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

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    static void EthFwBoard_configTorrentClks1(void)
    {
    uint32_t moduleId;
    uint32_t clkId;
    uint32_t clkRateHz;
    moduleId = TISCI_DEV_SERDES_10G1;
    clkId = TISCI_DEV_SERDES_10G1_CORE_REF_CLK;
    clkRateHz = 100000000U;
    EnetAppUtils_clkRateSet(moduleId, clkId, clkRateHz);
    EnetAppUtils_setDeviceState(moduleId, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0U);
    }
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

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    Board_STATUS Board_serdesCfgSgmii_serdes1(void)
    {
    CSL_SerdesResult result;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLane0EnableParams = {0};
    printf("%s %d \n",__func__,__LINE__);
    memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));
    /* SGMII Config */
    serdesLane0EnableParams.serdesInstance = (CSL_SerdesInstance)CSL_TORRENT_SERDES1;
    serdesLane0EnableParams.baseAddr = CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE;
    serdesLane0EnableParams.refClock = CSL_SERDES_REF_CLOCK_100M;
    serdesLane0EnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT0;
    serdesLane0EnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;
    serdesLane0EnableParams.numLanes = 0x2;
    serdesLane0EnableParams.laneMask = 0x3;
    serdesLane0EnableParams.SSC_mode = CSL_SERDES_NO_SSC;
    serdesLane0EnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;
    serdesLane0EnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane0EnableParams.phyInstanceNum = BOARD_SERDES_LANE_SELECT_CPSW;
    serdesLane0EnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    The log is as follows:

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    [MCU2_0] 15.998196 s: PHY 29 is no alive
    [MCU2_0] 15.998221 s: PHY 30 is no alive
    [MCU2_0] 15.998250 s: EnetMcm_enablePorts() +to open MAC port: 3
    [MCU2_0] 15.998441 s: status reg:0x0
    [MCU2_0] 15.998482 s: CpswMacPort_setSgmiiInterface: MAC 4: SERDES PLL is not locked 0x0
    [MCU2_0] 15.998519 s: CpswMacPort_setSgmiiInterface:
    [MCU2_0] 15.998553 s: Assertion @ Line: 2201 in src/mod/cpsw_macport.c: false
    [MCU2_1] 2.475382 s: CIO: Init ... Done !!!
    [MCU2_1] 2.475433 s: ### CPU Frequency = 1000000000 Hz
    [MCU2_1] 2.475464 s: CPU is running FreeRTOS
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

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    /opt/vision_apps/vision_apps_init.sh
    root@j784s4-evm:~# [MCU2_0] 2.480101 s: CIO: Init ... Done !!!
    [MCU2_0] 2.480141 s: ### CPU Frequency = 1000000000 Hz
    [MCU2_0] 2.480171 s: CPU is running FreeRTOS
    [MCU2_0] 2.480191 s: APP: Init ... !!!
    [MCU2_0] 2.480211 s: SCICLIENT: Init ... !!!
    [MCU2_0] 2.480361 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
    [MCU2_0] 2.480395 s: SCICLIENT: DMSC FW revision 0x8
    [MCU2_0] 2.480423 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU2_0] 2.480453 s: SCICLIENT: Init ... Done !!!
    [MCU2_0] 2.480475 s: UDMA: Init ... !!!
    [MCU2_0] 2.481455 s: UDMA: Init ... Done !!!
    [MCU2_0] 2.481492 s: UDMA: Init ... !!!
    [MCU2_0] 2.482020 s: UDMA: Init for CSITX/CSIRX ... Done !!!
    [MCU2_0] 2.482071 s: MEM: Init ... !!!
    [MCU2_0] 2.482105 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e2000000 of size 16777216 bytes !!!
    [MCU2_0] 2.482164 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 60000000 of size 262144 bytes !!!
    [MCU2_0] 2.482216 s: MEM: Init ... Done !!!
    [MCU2_0] 2.482238 s: IPC: Init ... !!!
    [MCU2_0] 2.482286 s: IPC: 11 CPUs participating in IPC !!!
    [MCU2_0] 2.482328 s: IPC: Waiting for HLOS to be ready ... !!!
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Thanks and regards,

    Cherry

  • Hi,

    Please correct the following configuration form "Board_serdesCfgSgmii_serdes1"

    - serdesLane0EnableParams.numLanes = 0x2;
    - serdesLane0EnableParams.laneMask = 0x3;

    + serdesLane0EnableParams.numLanes = 0x;1 // one lane select
    + serdesLane0EnableParams.laneMask = 0x2; //Lane1 enable

    - serdesLane0EnableParams.phyInstanceNum    = BOARD_SERDES_LANE_SELECT_CPSW;
    + serdesLane0EnableParams.phyInstanceNum    = 0; // It is IP for IP instance select in SerDes Lane only when same SerDes lane has two ethernet ports configurations it will be vary as per port being used . (Ex: SerDes2 Lane has Port-1(IP1) and Poer-7 (IP0), default Port1 is enabled from SerDes2 so it is set to 1)

    Also, remove "CSL_serdesIPSelect" calling for all lanes other than Lane1 (Port-4 enable from SerDes1).

    Can you please check with above modifications.

    Best Regards,
    Sudheer

  • Hi Sudheer,

    The customer has made the following changes:

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    Board_STATUS Board_CfgSgmii_serdes1(void)
    {
    CSL_SerdesResult result;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLane0EnableParams = {0};
    printf("%s %d \n",__func__,__LINE__);
    memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));
    /* SGMII Config */
    serdesLane0EnableParams.serdesInstance = (CSL_SerdesInstance)CSL_TORRENT_SERDES1;
    serdesLane0EnableParams.baseAddr = CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE;
    serdesLane0EnableParams.refClock = CSL_SERDES_REF_CLOCK_100M;
    serdesLane0EnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT0;
    serdesLane0EnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;
    serdesLane0EnableParams.numLanes = 0x1;
    serdesLane0EnableParams.laneMask = 0x2;
    serdesLane0EnableParams.SSC_mode = CSL_SERDES_NO_SSC;
    serdesLane0EnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;
    serdesLane0EnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane0EnableParams.phyInstanceNum = 0;//BOARD_SERDES_LANE_SELECT_CPSW;
    serdesLane0EnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    With the above modifications, it seems there isn't the print of PLL.

    1) Configure port 5 6 7 8 below code on serdes2 lane 0-3:

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    static Board_STATUS Board_CfgSgmii_serdes2(void)
    {
    CSL_SerdesResult result;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLane0EnableParams = {0};
    memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));
    /* SGMII Config */
    serdesLane0EnableParams.serdesInstance = (CSL_SerdesInstance)CSL_TORRENT_SERDES2;
    serdesLane0EnableParams.baseAddr = CSL_WIZ16B8M4CT3_2_WIZ16B8M4CT3_BASE;
    serdesLane0EnableParams.refClock = CSL_SERDES_REF_CLOCK_100M;
    serdesLane0EnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT0;
    serdesLane0EnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;
    serdesLane0EnableParams.numLanes = 0x4;
    serdesLane0EnableParams.laneMask = 0xf;
    serdesLane0EnableParams.SSC_mode = CSL_SERDES_NO_SSC;
    serdesLane0EnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;
    serdesLane0EnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane0EnableParams.phyInstanceNum = 0;//SERDES_LANE_SELECT_CPSW;
    serdesLane0EnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    2) How to make sure the serdes configuration is successful? Is the configuration successful without the following print?

    CpswMacPort_setSgmiiInterface: Mac 5: SerDes PLL is not locked 

    Thanks and regards,

    Cherry

  • Hi,

    You have to add below for all lanes. In case of Board_CfgSgmii_serdes2() it is missing for Lane2, Lane3.

    serdesLane0EnableParams.laneCtrlRate[1] = CSL_SERDES_LANE_FULL_RATE;
    serdesLane0EnableParams.loopbackMode[1] = CSL_SERDES_LOOPBACK_DISABLED;

    Also, make sure that SerDes clock is configured similar to "EthFwBoard_configTorrentClks1()".

    2) How to make sure the serdes configuration is successful? Is the configuration successful without the following print?

    CpswMacPort_setSgmiiInterface: Mac 5: SerDes PLL is not locked 

    If phy is connected to Link partner, will get Link Up message. It will confirm the configuration fine.
    We can check SerDes registers to confirm configuration was fine or not. If no prints like No PLL lock it might be locked.

    Best Regards,
    Sudheer

  • Hi Sudheer,

    Could you help check are the following modifications correct?

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    static Board_STATUS Board_CfgSgmii_serdes2(void)
    {
    CSL_SerdesResult result;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLane0EnableParams = {0};
    memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));
    /* SGMII Config */
    serdesLane0EnableParams.serdesInstance = (CSL_SerdesInstance)CSL_TORRENT_SERDES2;
    serdesLane0EnableParams.baseAddr = CSL_WIZ16B8M4CT3_2_WIZ16B8M4CT3_BASE;
    serdesLane0EnableParams.refClock = CSL_SERDES_REF_CLOCK_100M;
    serdesLane0EnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT0;
    serdesLane0EnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;
    serdesLane0EnableParams.numLanes = 0x4;
    serdesLane0EnableParams.laneMask = 0xf;
    serdesLane0EnableParams.SSC_mode = CSL_SERDES_NO_SSC;
    serdesLane0EnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;
    serdesLane0EnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane0EnableParams.phyInstanceNum = 0;//SERDES_LANE_SELECT_CPSW;
    serdesLane0EnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Thanks and regards,

    Cherry

  • Hi,

    Could you help check are the following modifications correct?

    Above attached text file with SerDes configuration is correct for configuring the port 5 6 7 8 in SGMII Mode.

    Best Regards,
    Sudheer

  • Hi Sudheer,

    Serdes1 lane 1 is already be linked, but it still cannot ping.

    The differential signals of TX, Rx are as follows:

    Does the following code configuration affect the DHCP or ping packet flow? 

    \ti-processor-sdk-rtos-j784s4-evm-08_06_00_14\vision_apps\utils\ethfw\src\app_ethfw_freertos.c

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    static EthFw_VirtPortCfg gEthApp_virtPortCfg[] =
    {
    {
    .remoteCoreId = IPC_MPU1_0,
    .portId = ETHREMOTECFG_SWITCH_PORT_0,
    },
    {
    .remoteCoreId = IPC_MCU2_1,
    .portId = ETHREMOTECFG_SWITCH_PORT_1,
    },
    {
    .remoteCoreId = IPC_MPU1_0,
    .portId = ETHREMOTECFG_MAC_PORT_5,
    },
    {
    .remoteCoreId = IPC_MCU2_1,
    .portId = ETHREMOTECFG_MAC_PORT_4,
    },
    };
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Thanks and regards,

    Cherry

  • Hi,

    Serdes1 lane 1 is already be linked, but it still cannot ping.

    It seems Port-4 is link up and no PLL issue, but from below configuration it seems like Port-4 is mapped to MCU2_1 RTOS client as MAC only port.
    DHCP enable or disable is in control of MCU2_1 client application, by default DHCP is enabled, you can connect Port-4 to DHCP network and check IP used in DHCP list then ping from external same network to Port-4 IP.


    {
    .remoteCoreId = IPC_MCU2_1,
    .portId = ETHREMOTECFG_MAC_PORT_4,
    },


    If you don't want to map Port-4 as MAC only port then you can comment below and build the application, so that Port-4 will be part of switch interfaces, you can access even from A72 virtual switch port interface.

    Best Regards,
    Sudheer

  • Hi Sudheer,

    DHCP enable or disable is in control of MCU2_1 client application, by default DHCP is enabled, you can connect Port-4 to DHCP network and check IP used in DHCP list then ping from external same network to Port-4 IP

    The dhcp cannot get the IP, when the mcu2-1 is set to static ip, the connection with the PC on the same network segment cannot be pinged.

    Under normal circumstances, mcu2-1 ->dhcp->routing can obtain IP, and linux a72 can use ifconfig to view IP

    Do you mean the following (example)

    {
    .remoteCoreId = IPC_MCU2_1,
    .portId = ETHREMOTECFG_MAC_PORT_4,
    },

    portId = ETHREMOTECFG_MAC_PORT_4Can such a setting disconnect ETHREMOTECFG_MAC_PORT_4 from the data of the external PHY?

    But when the customer comments out the following

    {
    .remoteCoreId = IPC_MPU1_0,
    .portId = ETHREMOTECFG_MAC_PORT_5,
    },
    {
    .remoteCoreId = IPC_MCU2_1,
    .portId = ETHREMOTECFG_MAC_PORT_4,
    },

    The customer is testing in a72 linux, use ifconfig eth0 xx.xx.xx.xx up to ping the external network, and it works.

    Does he need to comment out the following when he needs to use a72 to ping packets?

    {
    .remoteCoreId = IPC_MPU1_0,
    .portId = ETHREMOTECFG_MAC_PORT_5,
    },
    {
    .remoteCoreId = IPC_MCU2_1,
    .portId = ETHREMOTECFG_MAC_PORT_4,

    Regards,

    Annie

  • Hi,

    Does he need to comment out the following when he needs to use a72 to ping packets?

    {
    .remoteCoreId = IPC_MPU1_0,
    .portId = ETHREMOTECFG_MAC_PORT_5,
    },
    {
    .remoteCoreId = IPC_MCU2_1,
    .portId = ETHREMOTECFG_MAC_PORT_4,

    Above configuration is MAC only Ports, so these ports will not be part of switch network.
    If you want test these ports, we have connect external PC/network directly to these ports.

    Also, from above Port-5 is mapped to A72, where as Port-4 is mapped to MCU2_1 core.
    If Linux is running in A72, we need to map same Port-5 as MAC only port in device tree files, refer to FAQ [How to add/map MAC only Port to A72] for better understanding.
    Also refer to FAQ [ How to change MAC only mapped to A72].

    As Port-4 is mapped to MCU2_1 core as MAC only Port, A72 can't ping.

    If you want all ports to be part of switch and to use from A72 virtual switch interface, you have to comment out above.

    Best Regards,
    Sudheer