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TDA4AH-Q1: What is the difference between the Security Management System (SMS) and the Device Management & Security Control (DMSC)

Paul D7
Prodigy 30 points
Part Number: TDA4AH-Q1
Other Parts Discussed in Thread: TDA4VL, TDA4VH

1. What is the difference between the Security Management System (SMS) ( referenced in boot section ) and the Device Management & Security Control (DMSC) referenced in the Power Management and other areas of the TRM  ? 

           They both seem to have two cores : 1 for a TI firmware and a secondary core 

          Are they the same thing ? 

2. Is there a way to program the secondary core of the SMS or DMSC, with our own code  ? 

  • +1
    TI__Guru** 113475 points

    Hi Paul,

    1. SMS is the security subsystem present in TDA4VH/TDA4AH and TDA4VL/TDA4AL SoCs. This is the second-generation security subsystem on TDA4 devices, and has two Cortex-M4 cores. DMSC is the first-generation security subsystem, and it only has a single Cortex-M3 core. One core (Core 0) within the the SMS is reserved to run the TI Foundation Security (TIFS) firmware, while the second core is a free core for customer security stacks.

    The TI-SCI documentation may not have been updated to distinguish DMSC and SMS in every chapter.

    2. Yes. The second core in SMS (called the HSM Core) is meant for third-party security stacks and customization. 

    regards

    Suman

  • 0 in reply to Suman Anna
    Prodigy 30 points

    Hi Suman, 

    Thank you very much for confirming this situation. 

    Do you know if there is any documentation on how to program the second core ?

    Best Regards 

    Paul 

  • 0 in reply to Paul D7
    TI__Guru** 113475 points

    Hi Paul,

    Are you working with a third-party Security HSM stack vendor or trying to write software on your own?

    This is a standard Cortex-M4 core with some IRAM and DRAM. The HSM firmware is all expected to be running out of these memories, and the binary is expected to be a flat binary. The HSM firmware is expected to be authenticated and booted using the TIFS firmware using a Processor Boot API.

    Please refer to the ARM Cortex-M4 TRM for bootstrapping details. 

    TI recommends the IPC with the HSM core to be implemented over Secure Proxy using a protocol similar to TI-SCI.

    regards

    Suman

  • +1 in reply to Suman Anna
    Prodigy 30 points

    Hi Suman, 

    Thanks for the reply, 

    yes , we have a security HSM and will want to load our code onto the second core. 

    I will try to find the documentation on how to program and boot the M4, but I did not see this yet in the TRM. 

    BR
    Paul 

  • 0 in reply to Paul D7
    TI__Guru** 113475 points

    Hi Paul,

    The PDK SBL in RTOS SDK supports booting of the HSM core starting from SDK 8.5 onwards. The HSM M4 is treated like the other processors (for now) and booted as part of the combined 'app' image. The TI-SCI Processor Boot Control messages are used to boot the HSM M4 core using the TIFS core. 

    Please see the 5.2.9. HSM Boot section of the RTOS SDK documentation for combining the images. The TI-SCI messages are described in the Processor Boot Management TISCI Description section of the TI-SCI documentation.

    There is no support for booting the HSM core if using Linux U-Boot.

    regards

    Suman