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AM68A: Inquery about PCB Fabrication Note

Jack
Mastermind 9145 points
Part Number: AM68A
Other Parts Discussed in Thread: SK-AM68, AM68

Hi TI 

There'e three questions while customer review PCB Fabriction Note attached below.

[Q1] The note contains information about BACK DRILL (17. Backdrilling to be done from L12 to L04).

There are 16 NETs using 4 Layer to 12 Layer BACKDRILL, not on the AM68A SoC side, only on the bottom of LPDDR4.

DDR0_CA0~DDR1_CA5, DDR0_CK_T,DDR0_CK_C : LPDDR4 0 : 8ea Nets
DDR1_CA0~DDR1_CA5, DDR1_CK_T,DDR1_CK_C : LPDDR4 1 : 8ea Nets

Please check if the BACK DRILLING work of the NETs must be carried out.

[Q2] 2. Also, there is no clear mention of PCB material in Fabrication Note.
Is it possible to make a PCB with FR4? Or please check if I should use a PCB with a special material.

[Q3] 3. I cannot download AM68A SoC's DESIGN GUIDE from the homepage (ti.com ).
Please deliver the PCB Design Guide data for AM68A SoC.

I am only able to see the following docus.

* Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. E)

https://www.ti.com/lit/an/spracn9e/spracn9e.pdf?ts=1686585291117&ref_url=https%253A%252F%252Fwww.google.com%252F

 

* Jacinto 7 High-Speed Interface Layout Guidelines

https://www.ti.com/lit/an/spracp4/spracp4.pdf?ts=1686621628329&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTDA4VH-Q1

PROC131E1_FAB_Note.pdf

Thanks

Best Regards, 

Jack

  • 0
    TI__Guru 52335 points

    Q1:  For the SK-AM68 design, the back-drill is required to remove the via stub at the end of the T-branch signals near the memories (for the CA, CLK nets).  Yes this was required to improve signal integrity when operating at the highest data rates.

    Q2: The SK-AM68 board uses ISOLA I-Speed material.  Early Jacinto7 device simulations indicated FR4 could be used and still meet highest data rates if all PCB recommendations are followed.  However - TI's testing/validation efforts have been done using the I-Speed material.  Recommendation is to perform 3D simulations on your design and make decision on PCB material based on your results.  (Safest approach to achieve max rate is to follow TI's design)

    Q3:  I'm sorry, which document are you requesting for AM68?  I'm not familiar with AM68 PCB Design guide.  The links you provided for the Jacinto7 LPDDR and High Speed Guidelines do apply to the AM68 device.

  • 0 in reply to Robert Eschler
    Mastermind 9145 points

    Thank you Reobert, 

    Regarding AM68 PCB design guide, We'd appreciate if you provide us with genral PCB guideline of AM68A if available rather than my link found above.

  • 0 in reply to Jack
    TI__Guru 52335 points

    There is not a specific PCB guideline for AM68A.  The document links provided are for entire Jacinto7 family, and this includes AM68A.