AM625: The GPMC issue for AM6254

Hello Zhang Liang

Thank you for the query.

Please provide a bloc diagram of the interface approach you are considering.

Regards,

Sreenivasa

i Kallikppa,

Pleaes refer to the attach(Page 4 and Page 9) , thanks.

TI_o10_20230414_Litran.pdf

Hello Zhang Liang

Thank you for the inputs.

We have one GPMC instance as below 

6.3.11 GPMC
6.3.11.1 MAIN Domain
Table 6-25. GPMC0 Signal Descriptions

I am not able to understand the reason to connect the GPMC signals to the LCD signals and ths use case.

I cant see the FPGA - that you mentioned FPGA in your initial message.

I would suggest sharing a handwritten diagram to show the interface approach.

Regards,

Sreenivasa

Hi, Kallikuppa,

Please refer to the below picture, thanks.

Hello Zhang Liang

Kallikuppa Sreenivasa said:

I am not able to understand the reason to connect the GPMC signals to the LCD signals and ths use case.

Any thoughts please.

Regards,

Sreenivasa

Hi Kallikuppa,

I don't know what is the LCD, we only want to know the GPMP Maximum driving capacity, thanks.

Hello Zhang Liang

Thank you.

Please refer to the below section of the datasheet

7.11.5.11 GPMC

Does the FPGA need a clock for the interface?

I guess the NAND and the SRAM do not need the clock.

Regards,

Sreenivasa

Hi,

Yes, the NAND and SRAM don't need to the clock.

Hello Zhang Liang

Thank you for the reply.

Kallikuppa Sreenivasa said:

Does the FPGA need a clock for the interface?

Any thoughts please.

The diagram you have provided does not  include the planned interface approach.

Regards,

Sreenivasa

Hi,

No need the Clock, thanks.