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Interrupts on TMS320C6745

Gemaskerde_Sopbeen
Prodigy 10 points


Hi

I've written an industrial application on a C6745 that uses the McASP port. Being a safety critical device, I cannot use software not written by us (e.g. DSP/BIOS, CSL (if one existed), etc.). It's the first time my company uses a C6000 DSP.

My problem is with the CPU Interrupts. I can't find info on how to set up and enable / disable the CPU Interrupts. The Megamodule events are well documented and easy to map to CPU interrupts, but after that there's not much to go on.

The CPU user guide mentions the CPU interrupt registers and their contents, but do not tell you how to access them in C, what their addresses are, and so on. The device specific datasheet makes almost no mention of the CPU interrupts.

I've assigned the McASP event (No 61) to INT4 of the CPU. I basically need to be able to globally enable / disable the interrupts, as well as enable / disable INT4. I've copied a interrupt vector table from a C64+ project, and from the CPU user guide it looks very similar.

Any help or a pointer to the right documentation would be appreciated.

Thanks!

  • 0
    TI__Guru*** 125430 points

    The overall process is something like this:

    • Map event (0-127) to CPU interrupt (4-15) through the INTMUXn registers
    • Write your ISR using the interrupt keyword.
    • Create a vector table with branch to your ISR
    • Enable corresponding interrupt in IER register
    • Enable NMIE (one-time, can never be disabled) and GIE

    The registers INTMUX1-3 are memory mapped registers.  Their address and description is given in the Megamodule Reference Guide.  For example, if you wanted to assign McASP event (#61) to INT4 you could do the following:

    #define INTMUX1  (*(volatile unsigned int*)0x01800104)

    INTMUX1 &= ~0xFF; // clear out INTSEL4 field

    INTMUX1 |= 61;  // INTSEL4=61

    You would then need to setup an interrupt vector table.  See vectors.asm in the attached project.  Make sure you have .nocmp in the asm file so that the instructions don't get compacted.  In main the ISTP register needs to point to that vector table.

    The CPU registers get accessed by doing something like:

    extern cregister volatile unsigned int ISTP;

    Make sure you write your ISR with the interrupt keyword, e.g.:

    interrupt void my_isr()

    6455 Starter Project.zip