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DRA829V: Exception by ECC error

Hideaki Matsumoto
Genius 9765 points

Part Number: DRA829V

Hi,

We've received some questions below from my customer. Could you please answer them ?

Let me ask you five questions about ECC.
(1) Does an exception occur when an ECC2bit error occurs?
(2) If an exception does not occur when an ECC2Bit error occurs, is there a way to forcibly generate an exception?
(3) Does an exception occur when an ECC multi 1-bit error occurs?
(4) If an exception does not occur when an ECC multi 1-bit error occurs, is there a way to forcibly generate an exception?
(5) If an ECC multi 1-bit error occurs, will the error information that occurred in two places be accumulated in ① and ② as two error log information?

①DDRSS_ECC_1B_ERR_ADR_LOG_REG (*1)
②DDRSS_ECC_1B_ERR_MSK_LOG_REG (*2)
*1: "4.1.45" in J721E_regisers3.pdf
*2: "4.1.46" in J721E_regisers3.pdf

Regards,
Hideaki

  • 0
    TI__Guru 53501 points

    Hi Hideaki,

    Hideaki Matsumoto said:
    Does an exception occur when an ECC2bit error occurs?
    Hideaki Matsumoto said:
    Does an exception occur when an ECC multi 1-bit error occurs?

    If the ECC instances, ESM for the ECC errors and the ECC self test callbacks are initialized before error injection, the callback is triggered. Is this what you are asking about?

    Hideaki Matsumoto said:
    If an ECC multi 1-bit error occurs, will the error information that occurred in two places be accumulated in ① and ② as two error log information?

    This question seems to be referring to DDR ECC errors for DDR inline-ECC which is not done through ECC aggregator. Are these questions all related to DDR inline ECC?

    Thanks,

    Josiitaa

  • 0 in reply to Josiitaa RL
    TI__Genius 9765 points

    Hi Josiitaa,

    Thank you for your reply.

    Josiitaa RL said:
    If the ECC instances, ESM for the ECC errors and the ECC self test callbacks are initialized before error injection, the callback is triggered. Is this what you are asking about?

    No it's not.
    Your answer seems to describe the conditions under which an ECC error interrupt occurs.
    The question here is whether an exception such as a data abort occurs, apart from the occurrence of an interrupt such as an ECC2bit error.
    Based on this, please answer (1) to (4) as well.

    Josiitaa RL said:
    This question seems to be referring to DDR ECC errors for DDR inline-ECC which is not done through ECC aggregator. Are these questions all related to DDR inline ECC?

    Yes. They are all related DDR inline ECC.

    Please help to answer their questions.

    Regards,
    Hideaki

  • 0 in reply to Hideaki Matsumoto
    TI__Guru 53501 points

    Hi,

    Hideaki Matsumoto said:
    (1) Does an exception occur when an ECC2bit error occurs?
    (2) If an exception does not occur when an ECC2Bit error occurs, is there a way to forcibly generate an exception?
    (3) Does an exception occur when an ECC multi 1-bit error occurs?
    (4) If an exception does not occur when an ECC multi 1-bit error occurs, is there a way to forcibly generate an exception?

    No, there are no exceptions such as a data abort that occurs when a 2bit or multi 1bit error occurs. The error can be handled by modifying the code in the ISR callback or exception handler but triggering an abort does not occur as an exception is a CPU state and has nothing to do with ECC memory regions.

    Hideaki Matsumoto said:
    (5) If an ECC multi 1-bit error occurs, will the error information that occurred in two places be accumulated in ① and ② as two error log information?

    Single error correction double error detection (SECDED) ECC is calculated over 64-bit data quanta. For every 512-byte data block 64 bytes of ECC is stored inline. ECC memory is therefore viewed as blocks and the block address location is recorded in a the DDRSS_ECC_1B_ERR_ADR_LOG_REG. The number of 1-bit errors are also counted and recorded in a register, in case of multi 1-bit errors.

    Thanks,

    Josiitaa