Hi, I need you help.
The problem is : Dm6446 VPFE can't read front data [CCD0..CCD7] , the pixel clk is 12MHz, the data is enter VPFE at the falling edge. I don't use external HD and VD signal to sync, but I use VPSS internal HD and VD signal to sync, is it possilble? when I see in DDR2 address 0x82000000(VPFE_CCDC_SDR_ADDR) ， the data is not refresh when I move CIS (Front analog sensor), but the oscilloscope show the data is change with CIS move , what is the problem? who can help me? my Email is caoshanyou@163.com. Thank you.
The following is code in CCS3.3, it is used for initializating VPFE.
void VPFE_CCDC_RawInit(void)
{
VPFE_CCDC_SYN_MODE |= (1<<0);/*VD HD output 0*/
VPFE_CCDC_SYN_MODE |= (1<<16);/*VD HD enable*/
VPFE_CCDC_SYN_MODE &= ~(1<<5);/*C_WE enable */
VPFE_CCDC_SYN_MODE &= ~(1<<2);/*VD POL 0*/
VPFE_CCDC_SYN_MODE &= ~(1<<3);/*HD POL 0*/
VPFE_CCDC_SYN_MODE |= (1<<7);/*field mode 0 progressive*/
VPFE_CCDC_SYN_MODE |= (1<<1);/*FLDOUT output*/
VPFE_CCDC_SYN_MODE &= ~(1<<4);/*FLD POL 1 negative*/
//-->>>---------CCD[7:0]->A2--------->>>>>
// VPSS_CLK_CTRL = 0x00000018; // Enable DAC and VENC clock, both at 27 MHz
VPFE_CCDC_SYN_MODE &= ~(1<<6);/*Data polarity*/
VPFE_CCDC_SYN_MODE |= (1<<10);/*Data size 8 bits*/
VPFE_CCDC_SYN_MODE |= (1<<9);
VPFE_CCDC_SYN_MODE |= (1<<8);
VPFE_CCDC_SYN_MODE |= (1<<11);/*Pack8*/
//-->>>---------A2->B-------->>>>>
VPFE_CCDC_SYN_MODE &= ~(1<<13);/*INPMOD：CCD RAW Data Mode*/
VPFE_CCDC_SYN_MODE &= ~(1<<12);
VPFE_CCDC_CLAMP &= ~(1<<31);/*clamp.clamp en 0*/
VPFE_CCDC_DCSUB = 0;
VPFE_CCDC_COLPTN = 0xEE44EE44;/*COLPTN*/
VPFE_CCDC_BLKCMP = 0x01;/*BLKCMP*/
VPFE_CCDC_FPC &= ~(1<<15);/*FPCEN = 0*/
//-->>>---------B->C------->>>>>
VPFE_CCDC_FMTCFG &= ~(1<<15);/*VPEN = 0*/
VPFE_CCDC_FMTCFG &= ~(1<<14);/*FMTCFG.VPIN Bit:15-6*/
VPFE_CCDC_FMTCFG &= ~(1<<13);
VPFE_CCDC_FMTCFG &= ~(1<<12);
VPFE_CCDC_FMT_HORZ = 0x00000088;
VPFE_CCDC_FMT_VERT = 0x00000088;
VPFE_CCDC_VP_OUT = 0x041A2D00;
VPFE_CCDC_SYN_MODE &= ~(1<<18);/*VP2SDR disable*/
//-->>>---------C->DDR2------->>>>>
VPFE_CCDC_HORZ_INFO = 0x00080064;/*HORZ_INFO.SPH & NPH*/
VPFE_CCDC_VERT_START = 0x00010001;/*VERT_START.SLV0、1*/
VPFE_CCDC_VERT_LINES = 0x00000032;/*VERT_LINES.NLV*/
VPFE_CCDC_SYN_MODE &= ~(1<<14);/*SYN_MODE.LPF disable*/
VPFE_CCDC_CULLING = 0xFFFF00FF;/*CULLING_CULHEVN CULHODD CULV disable*/
VPFE_CCDC_ALAW |= (1<<3); /*ALAW.CCDTBL enable*/
VPFE_CCDC_ALAW |= (1<<2);/*ALAW.GWID: 0~9Bit*/
VPFE_CCDC_ALAW |= (1<<1);
VPFE_CCDC_ALAW &= ~(1<<0);
VPFE_CCDC_SYN_MODE &= ~(1<<19);/*SYN_MODE.SDR2RSZ disable*/
VPFE_CCDC_HSIZE_OFF = 0xFF;
VPFE_CCDC_SDOFST = 0x00000000;/*SDOOFT*/
VPFE_CCDC_SYN_MODE |= (1<<17);/*SYN_MODE.WEN enable*/
//other regs
VPFE_CCDC_SDR_ADDR = 0x82000000;
VPFE_CCDC_PCR = 1;/*enable */
}
