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TDA4VM: Connection between GPIO modules and CBASS

Thomas Dedler
Intellectual 270 points
Part Number: TDA4VM

Hello TI,

I have a question regarding how the GPIO modules are connected to the internal CBASS bus. From previous discussions I know that CBA is implemented as a crossbar switch. Thereto communication between two bus nodes can take place in parallel without interferences.

For GPIO, the question is which "type of instances" are connected separately to the bus so they can be accessed in parallel?

With "type of instances" I mean the following:

- physical instances for the external pins (WKUP_GPIO0, GPIO0 and GPIO1, in the overview below on the right side)

- virtual instances (WKUP_GPIO0-1, GPIO0-7, below on the left).  

In the connectivity matrix in the TRM it looks like on the bus only the physical instances are connected separately:

 

But in the same chapter, the virtual modules are listed for the firewall settings:

So if I want to distribute the GPIOs for two different cores in a way that accesses do not cause interferences, what do I have to do?

a) Assign the GPIOs of one core to the physical instance GPIO0, and the other to GPIO1 and/or WKUP_GPIO0

b) Assign the GPIOs to pads regardless of the core that uses it and then map them with the PADCONFIG register to different virtual instances  

Best regards

Thomas

  • 0
    Intellectual 270 points

    Hello TI,
    any updates for this topic?
    Is there any document with a complete list of independent slaves on the CBASS (i.e. which can be accessed in parallel by different masters)?

  • 0 in reply to Thomas Dedler
    Intellectual 270 points

    Hello,

    still waiting for some information regarding access to GPIOs

  • +1 in reply to Thomas Dedler
    TI__Mastermind 23695 points

    Hello Thomas,

    Sorry for the delay, I was asked to review this a couple weeks back just before I was out for vacation.

    Their are 10 GPIO IP blocks, 8 hung off of the main_infra cbass with their segment interface clocks @125MHz and 2 hung off the wkup_cbass @166MHz.  Each GPIO block has multiple GPIOs.  Accesses within an IP block could compete with each other, accesses to individual blocks should be able to flow independently through the SCR network.

    I am not understanding your question about contention on the output muxing side, it will be assigned to a pin or not.  Some brief contention might happen on the input side to a given GPIO IP block.

    Regards,
    Richard W.
  • 0 in reply to Richard Woodruff
    Intellectual 270 points

    Hi Richard,

    Thanks for your answer, now its clearer.

    The confusing thing was Table 3-18 in the TRM where only 2 (and not 8) GPIO blocks are mentioned for the MAIN domain, so I was not sure what is relevant for access from CBASS.

    But you made it clear that only the GPIO IP blocks are relevant.

    Regards

    Thomas