Other Parts Discussed in Thread: DRA829, TDA4VM
Dear TI experts,
To demonstrate performance and determinism, we need to know internal infrastructure details of the J7 interconnect (CBASS0, MCU_CBASS, WKUP_CBASS, INFRA_CBASS, MSMC, NAVSS "Local Interconnect" and "PSI-L", etc...!).
In particular, information about interconnection and hierarchy of bus-nodes up to Bridges and SCRs levels (or even lower level - see spraan7), including their bus-width, -speed, -type, -protocol (VBUSP/M), their RT/NRT capabilities, the arbiters and their rules, internal FIFO buffering and transaction timing, (etc...!), is necessary. This is needed to identify potential bottle-necks and to mitigate them in advance, e.g. by software architecture / resource allocation / routing means set by configuration, in order to ensure freedom from interference for our specific use-cases.
In the J7 TRM spruil1c, the interconnect infrastructure is either roughly described (chapters 1.2, 3.1-3.2) or certain aspects are very precisely detailed (e.g. Master-Slave connections chap. 3.3.1, 3.3.2), but an intermediate view is missing.
I've found the document spraci6 for the AM65x processors, which contains a good basis for our needs even if not complete, but nothing for the Jacinto-7 (TDA4VM / DRA829).
Is there similar documents for the Jacinto-7 describing the infrastructure of the interconnect and its characteristics like specified above?
Many thanks in advance
Laurent
