AM6412: Layout Review of AM6412 and DDR

Pavan Kalyan

Part Number: AM6412

Hi,
We are Using AM6412 With one DDR.

I have attached the PIN Pair report of DDR and AM6412 Please go through the same and Kindly let us know if it's fine or Any modification required According to Length matching point of view.

Neck Length on Both sides is 22.25(Approx)
Note:- We have routed ADD_CTRL, BYTE0, BYTE1 class signals in the internal layers and AT(Termination) in the Top/Bottom

DDR_PIN PAIR REPORT.xlsx
Regards
Pavan

over 2 years ago

0 Kallikuppa Sreenivasa over 2 years ago

TI__Guru**** 196389 points

Hello Pavan,

Thank you for the query.

I am not sure if we support review of the layout. I am reassigning to the expert for this thoughts.

In the mean time, can you confirm you have followed the below design guide and also performed SI simulations.

https://www.ti.com/lit/an/spracu1a/spracu1a.pdf

Regards,

Sreenivasa

0 Pavan Kalyan over 2 years ago in reply to Kallikuppa Sreenivasa

Prodigy 225 points

Hi Sreenivasa,

Thank you for the response.

Please note that we have followed AM6412 schematic checklist :

https://www.ti.com/lit/an/spracu5b/spracu5b.pdf?ts=1687261707713&ref_url=https%253A%252F%252Fwww.google.com%252F
And For DDR layout Guidelines we have followed below document
https://www.ti.com/lit/an/spracu1a/spracu1a.pdf?ts=1687322066332

we have done the SI simulation with IBIS Model of AM6412 (Without timing model) and it is passed.

Regards
Pavan

+1 JJD over 2 years ago in reply to Pavan Kalyan

TI__Guru* 88000 points

Pavan, we don't do layout reviews, it is just too time consuming. Since you followed the app notes and performed simulations, you should be in good shape.

I did briefly look over the length report, and noticed one possible issue on UDQSn/p, these have a little too much skew. Ensure that all differential signals have very tight skew. Also double check skew between CK and addr/ctrl signals, and then DQS vs data signals within a byte. These looked ok on a cursory look, but i would double check.

Regards,

James

0 Pavan Kalyan over 2 years ago in reply to JJD

Prodigy 225 points

Hi James,
Thanks for your response.
Generally we do SI simulations for DDR with Timing models. we Just want to be sure since we are not having the timing model data. Sure we will double check the things from our side and we will implement your suggestions.

Regards
Pavan

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AM6412: Layout Review of AM6412 and DDR