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interrupt nesting hangs up very rarely

hiro10784
Intellectual 260 points

I want to enable nesting interrupt ,so descripted like below, but it's some times hangs (very rarely).

when it's hang. GIE in CSR is ='0'  indicated. but I can't recognized why it is.

please someone drop me any hint .


volatile int tint0_csr;
volatile int tint0_irp;
volatile int tint0_ier;

interrupt void int_timer0(void)
{
 int ttt;

 tint0_csr = CSR;  // here is GIE=0 automatically while ISR
 tint0_irp = IRP;
 tint0_ier = IER;

 INTR_GLOBAL_ENABLE(); // enable interrupt  for nesting

 // some processing code (demo. dummy)
 for(ttt=0;ttt<10;ttt++){
  asm(" nop");
  asm(" nop");
  asm(" nop");
  asm(" nop");
 }

 CSR = tint0_csr;  // restore register and disable interrupt
  IRP = tint0_irp;  // restore register
 IER = tint0_ier;  // restore register
}

 

  • 0
    TI__Mastermind 18130 points

    Might I ask why you are using nested interrupts? This is typically a dangerous practice as many things can go wrong. For example, keep in mind that every time you nest an interrupt that the stack size increases. As the number of nested interrupts so too does the stack. If you nest too many interrupts you can easily overflow the stack.

    Secondly please describe the "hang" you experience - where is the code stuck? Also, just for clarity which device are you using?

  • 0
    TI__Guru*** 125430 points

    Hiro,

    You need to have an additional line to disable interrupts.  I know that's the intent of the line where you restore CSR, but the documentation specifically says the following:

    spru733a Ch 5.6.2 said:

    Prior to returning from the interrupt service routine, the code must restore the
    registers saved above as follows:

    1) The GIE bit must be first cleared to 0
    2) The PGIE bit saved value must be restored
    3) The IRP (or NRP) saved value must be restored

    Although steps 2 and 3 above may be performed in any order, it is important
    that the GIE bit is cleared first. This means that the GIE and PGIE bits must
    be restored with separate writes to CSR. If these bits are not restored
    separately, then it is possible that the PGIE bit is overwritten by nested
    interrupt processing just as interrupts are being disabled.

     

  • 0 in reply to Brad Griffis
    TI__Guru*** 125430 points

    PS.  Based on your posts in the past I have assumed you are working on c671x or c672x.  Note that there are additional registers that would need to be saved if you were working on a 64x+ or 674x architecture.

  • 0 in reply to Brad Griffis
    Intellectual 260 points

    Very thanks griffis.

    I'm reached same conclusion last day, but I refered document that spru189f noticed not so good expression, I think.

    I'm working with C6701, if  working with c67+ chip, I not met with this pit . ;)

    finally, program works very well.