AM6412: ICSSG MDIO-manual-mode access to non TI PHY not working

Hi Dennis,

Will get back to you asap.

Thanks and regards,

Rimika

Hi Dennis,

Which SDK are you working with?

Thanks and Regards,

Rimika

Hi Rimika,

thanks for your response.
We are using SDK 8.4.0.17 for Profinet and 8.6.0 for ethernetip.

Dennis

Hi Dennis

The code for MDIO bit banging is already available as part of SDK AFAIK, have you already started to review the code to see if you can manipulate that to meet the timings for your PHY?

SDK documentation is here : AM64x MCU+ SDK: PRU-ICSS Firmware for MDIO Manual Mode (ti.com)

Thanks Mukul,

looks like I found the asm file here:

*/source/pru_io/firmware/common/mdio_macros.inc
*/examples/pru_io/mdio_fw/main.asm

But I can not find how this code is then integrated to:
source/industrial_comms/profinet_device/icss_fwhal/firmware/mii/profinet_irt_pru1_bin.h

Regards, Dennis

Hi Dennis, 

For rebuilding the project you can import the project from location <sdk_path>/examples/pru_io/mdio_fw/

Once you rebuild the project, mdio_fw_bin.h file gets generated in debug folder (in CCS). From this file you can copy contents of the generated firmware array to <sdk_path>\source\industrial_comms\profinet_device\icss_fwhal\firmware\mdio_fw_bin.h file.

Firmware details:

You can find the assembly macros that are used for communication with the PHYs in <sdk_path>/source/pru_io/firmware/common/mdio_macros.inc,
specifically: m_mdio_read, m_mdio_write macros

In these read/write macros, m_mdio_toggle_bit_lh is used to drive MCLK pin and we wait inside this macro for low and high pulse widths of clock, which is decided by value of MDIO_CLK_PERIOD_CONFIG (If you want to change communication frequency, change this constant)

Other timing requirements are handled by how and when the MCLK and MDATA pins are driven by the firmware, which you can check in these macros.

Thanks, Himanshu

Thanks Himanschu looks like this will help, I will give feedback when I have updates on this.

We managed to build the mdio_fw but it looks like it is statically compiled to the industrial fieldbus library, can you confirm this?

Hi Dennis, 

Yes, I think it will be part of the stack/library. 

You can still test out your PHY with your updated mdio_fw binary header file by reloading the TX_PRU0 core with it. Then you can make MDIO access requests to see if it is working after your changes. 

Sample code for loading application to TX_PRU0 core:

    /* ---------------------------------------------------------- */
    /* Program code to PRU Core;                                  */
    /* ---------------------------------------------------------- */
    status = PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_TX_PRU0);
    DebugP_assert(SystemP_SUCCESS == status);

    /* Load firmware. Write PRUFirmware code array to Pru IRAM memory */
    /* Code array will be in mdio_fw file */
    status = PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_TX_PRU(0), 0,
                       (uint32_t *) PRUFirmware, sizeof(PRUFirmware));
    DebugP_assert(status != 0);

    /* Reset core */
    status = PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_TX_PRU0);
    DebugP_assert(SystemP_SUCCESS == status);
    
    /* Pass value for emulated MDIO Base Address to R12 of TX_PRU core */
    CSL_REG32_WR(CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX0_IRAM_DEBUG_REGS_BASE + (4*12), 0x1ff00);

    /* Run firmware */
    status = PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_TX_PRU0);
    DebugP_assert(SystemP_SUCCESS == status);

Also, if possible, can you please share the differences you see between the MDIO signals with MDIO Spec and with bit-banging method so that I can help find what can be the issue. (Complete MDIO communication frame signal trace for both cases will be really helpful to point out the issue!)

One thing I see in the MDIO read/write functions, there is an extra clock pulse we send at the ending, might not be required with the PHY you are working with.

Code being used for that clock low pulse is in file - <sdk>/source/pru_io/firmware/common/mdio_macros.inc :

    mov     userAccessReg.w0, value                 ; Update Read Value
    m_mdio_clr_bit          "MCLK", baseAddr
    nopx    50                                      ; Give time for pull-up to work
    m_mdio_toggle_bit_lh    "MCLK", baseAddr        ; re-enable PHY Interrupt function

Lines 2,3,4 here clears and sets the MCLK line to create a low pulse.

Let me know if you need any help with this. 

Thanks, Himanshu

Thanks Himanshu,

when we reload the mdio fw to the PRU will the fieldbusstack still run fine after that?

And yes we will share the changes and differences when we have fixed the issue.

Regards, Dennis

Hi Dennis, 

Ideally it should work fine as TX_PRU acts as completely independent core emulating MDIO HW IP.
Still if somehow there are some issues, for debugging purpose using above approach of reloading the firmware, you should be able to test out if your modified MDIO firmware works fine with the ADI PHY, and then we can see how the required changes can get integrated within the stack.

BR, Himanshu