C6747 vs 6713 floating point performance (way slower)

Would this not be something the DSP BIOS configuration would set up? I do have L1P and L1D enabled, I tried with L2 disabled and enabled (128K), that part made no difference.

Thank you, I manually set up MAR196 for SDRAM and enabled 128K of L2 and that did the trick. But I am having cache coherence issues with EDMA. The 0x8 and 0xC are not making sense to me, as the MARxx bits are only one bit for enable. Which register are you referring too?

> The 0x8 and 0xC are not making sense to me, as the MARxx bits are only one bit for enable. Which register are you referring too?

As you already know, each MAR register represent a range of memory that it controls for enabling caching. See here:
http://tiexpressdsp.com/index.php/Enabling_64x%2B_Cache
On C6747, the L3 ram is at address 0x80000000 - 0x8001ffff and the external memory at: 0xC0000000 - 0xDFFFFFFF. You need to ensure that the MAR registers are set for the memory that you need to enable caching for. by 0x8 and 0xC I meant the L3 RAM and external memory and not really MAR bits. Sorry for confusion.

For cache coherence with EDMA, see the cache UG for details http://focus.ti.com/lit/ug/sprug82a/sprug82a.pdf. There are DSP-BIOS BCACHE module APIs that you can use for cache coherence
Gagan

try following code insert at a begin of program.

 CSR &= ~0x00000080;  

# I'm encounterd with C6727

Edmund,

I will give feedback about that. For now I created the page:

http://tiexpressdsp.com/index.php/C6747_Audio_Example_cache_configuration