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How to use the EMIF_A in the C6747?

liangxiao zhang
Expert 1430 points
Other Parts Discussed in Thread: CCSTUDIO

My CCS is CCStudio v3.3.I want to use EMIF_A in the C6747. EMIF_A connect with FPGA.

My questions as follows:

1,I should config EMIF_A what mode?is SDRAM?or FLASH?

2,How to config the EMIF_A regs?

3,when I read or write data to the FPGA,CE3(I use CE3 connct with FPGA) chang low a little time.But other Pins (WE,OE)is NO CHANGE.However I config the regs,it can not working.WHY?

  • 0
    TI__Mastermind 18130 points

    liangxiao zhang said:

    1,I should config EMIF_A what mode?is SDRAM?or FLASH?

    2,How to config the EMIF_A regs?

    This depends on how your FPGA is configured to communicate. The nice thing about FPGAs is that you can create an interface to communicate with virtually any peripheral on any device. If you prefer to program your FPGA to communicate as an SDRAM device that if perfectly fine (and may result in faster throughput as well). But the choice is all yours.

    liangxiao zhang said:
    3,when I read or write data to the FPGA,CE3(I use CE3 connct with FPGA) chang low a little time.But other Pins (WE,OE)is NO CHANGE.However I config the regs,it can not working.WHY?
    I couldn't say without more information. Can you include your EMIFA register configuration and some oscope/logic analyzer traces?

  • 0 in reply to TimHarron
    Expert 1430 points

    I just config

    #define AEMIF_BASE              0x68000000
    #define AEMIF_AWCCR             *( volatile Uint32* )( AEMIF_BASE + 0x04 )
    #define AEMIF_A1CR              *( volatile Uint32* )( AEMIF_BASE + 0x10 )
    #define AEMIF_A2CR              *( volatile Uint32* )( AEMIF_BASE + 0x14 )
    #define AEMIF_A3CR              *( volatile Uint32* )( AEMIF_BASE + 0x18 )
    #define AEMIF_A4CR              *( volatile Uint32* )( AEMIF_BASE + 0x1C )
    #define AEMIF_EIRR              *( volatile Uint32* )( AEMIF_BASE + 0x40 )
    #define AEMIF_EIMR              *( volatile Uint32* )( AEMIF_BASE + 0x44 )
    #define AEMIF_EIMSR             *( volatile Uint32* )( AEMIF_BASE + 0x48 )
    #define AEMIF_EIMCR             *( volatile Uint32* )( AEMIF_BASE + 0x4C )
    #define AEMIF_NANDFCR           *( volatile Uint32* )( AEMIF_BASE + 0x60 )
    #define AEMIF_NANDFSR           *( volatile Uint32* )( AEMIF_BASE + 0x64 )
    #define AEMIF_NANDECC2          *( volatile Uint32* )( AEMIF_BASE + 0x70 )
    #define AEMIF_NANDECC3          *( volatile Uint32* )( AEMIF_BASE + 0x74 )
    #define AEMIF_NANDECC4          *( volatile Uint32* )( AEMIF_BASE + 0x78 )
    #define AEMIF_NANDECC5          *( volatile Uint32* )( AEMIF_BASE + 0x7C )

    AEMIF_A2CR = 0x80300389;
    // AEMIF_NANDFCR |= 2;
    AEMIF_NANDFCR &= ~2;

    I just config  AEMIF_A2CR  and AEMIF_NANDFCR .I use CE3 connect with FPGA. is it right? If I am wrong ,how to config?

    When I read 0x62000008,CE3 go low for a little time,but OE\WE is NO CHANGE.all of EMIF_A is low.WHY?