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Help!!About EMIFA of C6747

sky10367
Prodigy 85 points
Other Parts Discussed in Thread: TMS320C6745

If a hardware system is designed like Figure 6-13 C6745/6747 Connection Diagram: SDRAM, NOR, NAND-----(P83,at TMS320C6745/6747 Floating-point Digital Signal Processor,TMS320C6745.pdf).the GPIO pins from GP4[0] to GP4[5] are used as the upper address lines. I choose SST39VF800A Flash made by SST.The steps to access the XOR Flash as follow:

1.System Configuration

#define PINMUX0V  0x00000000
#define PINMUX1V  0x00000000
#define PINMUX2V  0x00000000
#define PINMUX3V  0x00000000
#define PINMUX4V  0x00000000
#define PINMUX5V  0x88888888
#define PINMUX6V  0x88888888
#define PINMUX7V  0x00000000
#define PINMUX8V  0x20000000
#define PINMUX9V  0x00000002
#define PINMUX10V  0x00000000
#define PINMUX11V  0x00001100
#define PINMUX12V  0x88880000
#define PINMUX13V  0x11888888
#define PINMUX14V  0x11111111
#define PINMUX15V  0x11111111
#define PINMUX16V  0x11111111
#define PINMUX17V  0x11111111
#define PINMUX18V  0x11111111
#define PINMUX19V  0x00000001

 *(int *) KICK0R =0x83e70b13;
  *(int *) KICK1R =0x95A4F1E0;
  *(int *) PINMUX5 =PINMUX5V;
  *(int *) PINMUX6 =PINMUX6V;
  *(int *) PINMUX8 =PINMUX8V;
  *(int *) PINMUX9 =PINMUX9V;
  *(int *) PINMUX11 =PINMUX11V;
  *(int *) PINMUX12 =PINMUX12V;
  *(int *) PINMUX13 =PINMUX13V;
  *(int *) PINMUX14 =PINMUX14V;
  *(int *) PINMUX15 =PINMUX15V;
  *(int *) PINMUX16 =PINMUX16V;
  *(int *) PINMUX17 =PINMUX17V;
  *(int *) PINMUX18 =PINMUX18V;
  *(int *) PINMUX19 =PINMUX19V;
  *(int *) KICK1R =0x88888888;

2..configure thetregisters of CE2CFG and EMIFA_NANDFCR

 *(unsigned int *) CE2CFG =0x88644329;
 *(unsigned int *) EMIFA_NANDFCR &= ~1;

3. comfigure  GPIO pins from GP4[0] to GP4[5]

*(int *) DIR45 =0xFFFFFFC0;

4.enter and read flash software ID

#define Flash_Addr1  (unsigned int)( 0x60005555)
#define Flash_Addr2  (unsigned int)( 0x60002aaa)
#define GPIO_Addr    0x01E26064

*(unsigned  int *)(GPIO_Addr)=Flash_Addr1>>13;
    *(unsigned int *)(Flash_Addr1) =0x00aa;
 *(unsigned  int *)(GPIO_Addr)=Flash_Addr2>>13;
 *(unsigned int *)(Flash_Addr2) =0x0055;
 *(unsigned  int *)(GPIO_Addr)=Flash_Addr1>>13;
 *(unsigned int *)(Flash_Addr1) =0x0090;
    *(unsigned  int *)(GPIO_Addr)=0;
 Flash_Mv =*(unsigned int *) 0x60000000;
 Flash_Id =*(unsigned int *) 0x60000001;

Question:

Finally,DSP can not access the flash, I want to know what is wrong about the steps or the codes?

Thanks

sky

 

  • 0
    TI__Mastermind 18130 points

    Will you please elaborate a bit on what you mean by the "DSP can not access the flash?" Do the EMIF pins ever toggle or are they static? Depending on the behavior we can focus on a specific area.

  • 0 in reply to TimHarron
    Expert 1215 points

    I am basically doing the same thing with M29W800DB. My problem is that whatever and whereever I tried to write, it will not succeed. 

    For example, if I write to 0xAA to 0x60000AAA, the value at 0x60000AAA in memory window doesn't change. 

    if I do

     

        FlashWrite( ConvAddr(0x00555), (uCPUBusType)CMD(0x00AA) );  /* 1st Cycle */

        FlashWrite( ConvAddr(0x002AA), (uCPUBusType)CMD(0x0055) );  /* 2nd Cycle */

        FlashWrite( ConvAddr(0x00555), (uCPUBusType)CMD(0x0090) );  /* 3rd Cycle */

        *ucpDeviceId = FlashRead(0x1); //read device ID

    I always get a 0xFF.

     

  • 0 in reply to yl
    Prodigy 85 points

    I give you some suggestion.

    1.  test the CS[2:5] which you use,know if tha is low when read or write the Flash .

    2. check the signal of WRE and OE of EMIFA

    3. make sure the right configuration of PSC .

  • 0 in reply to sky10367
    Expert 1215 points

    Thanks.

    The CS2 (the one we are using), WE and RE all seem to be high, or maybe they went low for a short period of time but I could not see on scope. If the CS is indeed always high, what did I miss?

    The PSC are all on, 

        // PSC0
        PSC0_lPSC_enable(0, 0);
        PSC0_lPSC_enable(0, 1);
        PSC0_lPSC_enable(0, 2);
        PSC0_lPSC_enable(0, 3);  // EMIFA
        PSC0_lPSC_enable(0, 4);
        PSC0_lPSC_enable(0, 5);
        PSC0_lPSC_enable(0, 6);
        PSC0_lPSC_enable(0, 8);
        PSC0_lPSC_enable(0, 9);
        PSC0_lPSC_enable(0, 10);
        PSC0_lPSC_enable(0, 11);
        PSC0_lPSC_enable(0, 12);
        PSC0_lPSC_enable(0, 13);

    // PSC1
        PSC1_lPSC_enable(0, 1);
        PSC1_lPSC_enable(0, 2);
        PSC1_lPSC_enable(0, 3);
    PSC1_lPSC_enable(0, 4);
        PSC1_lPSC_enable(0, 5);
        PSC1_lPSC_enable(0, 6);  // EMIFB
        PSC1_lPSC_enable(0, 7);
        PSC1_lPSC_enable(0, 8);
        PSC1_lPSC_enable(0, 9);
        PSC1_lPSC_enable(0, 10);
        PSC1_lPSC_enable(0, 11);
        PSC1_lPSC_enable(0, 12);
        PSC1_lPSC_enable(0, 13);
        PSC1_lPSC_enable(0, 16);
        PSC1_lPSC_enable(0, 17);
        PSC1_lPSC_enable(0, 20);
        PSC1_lPSC_enable(0, 21);
        PSC1_lPSC_enable(0, 24);
        PSC1_lPSC_enable(0, 25);
        PSC1_lPSC_enable(0, 26);
        PSC1_lPSC_enable(0, 31);

  • 0 in reply to yl
    TI__Guru* 84110 points

    If CS is always high, then either the EMIF has not been configured correctly for this CSn space or else your memory access is not to the correct address range to access this CSn space.

  • 0 in reply to sky10367
    Expert 1430 points

    I have the same problem.

    when I use CS2,CS2 is low a little time.

    but the WRE and OE of EMIFA is always high.

    my questions have two.

    1,the WRE and OE of EMIFA is always high.but CS can change low.

    2,what is PSC.I do not find PSC.

  • 0 in reply to liangxiao zhang
    TI__Guru* 84110 points

    Your success will be greatest when you start with an EVM and the examples provided with it. This may be your path today, but it is not yet clear.

    liangxiao zhang said:

    when I use CS2,CS2 is low a little time.

    How is the EMIFA configured for the address range of CS2? What are the relevant register settings? What memory access do you perform to get the CS2 to go low? How long is "a little time"?

    liangxiao zhang said:

    1,the WRE and OE of EMIFA is always high.but CS can change low.

    During an asynchronous memory access that causes CS2 to go low, one or the other of WE and OE will go low for the time that you have programmed in the EMIF registers. There is a mistake in the register programming, or the pin configuration, or the board layout, or the wrong pins are being observed.

    liangxiao zhang said:

    2,what is PSC.I do not find PSC.

    Please download the C6747 datasheet sprs377 and search for PSC. There is a short description there. For more detail, download the System Reference Guide sprufk4 and find PSC in the table of contents. PSC is the Power and Sleep Controller.

  • 0 in reply to RandyP
    TI__Mastermind 18130 points

    RandyP said:

    If CS is always high, then either the EMIF has not been configured correctly for this CSn space or else your memory access is not to the correct address range to access this CSn space.

    This is a bit of a long-shot but you could also experience this behavior is L2 cache is enabled and the CPU is accessing cached memory.