AIF2 SERDES clocking, PHYsync and RADsync usage.

Hi,

here is the answer of  your question.

1. Yes. it can be left unconnected or pull down.

2. No just one time pulse is enough. pulse duration could be at least bigger than two byte clock cycles

   pulse doesn't have to be in sync with other event.

Regards,

Albert

Thanks Albert for your quick reply.

I have another query with respect to AIF2 clock.

From the documentation I could understand that the SYSCLK will be used by the AIF2 module. However in many places in the document it has been mentioned that OBSAI requires 307.2MHz and CPRI requires 245.76 MHz.

Does this clock frequency have any other significance apart from the SERDES clock? Because by using 307.2M we can achieve serdes rate of 6.144 Gbps by setting MPY= 20 and MPY=25 if we use 245.76 MHz. Why is that it has been insisted on using 245.76 MHz clock for CPRI?

For 6.144 Gbps CPRI what should be the SYSCLK to be used. Please clarify.

Thanks,

Khaleel

Khaleel,

You misunderstood about clock. CPRI only can support max 4.9 Gbps line rate . only OBSAI support 6 Gbps line rate but the BW for payload is same becasue OBSAI has larger overhead than CPRI (OBSAI header part make this BW consumption)

OBSAI : 307.2 MHz byte clock  =  122.88 MHz (sys clock) * 25x (SERDES PLL) / 10 (8/10 bit decoding)

CPRI : 245.76 MHz byte clock = 122.88 MHz (sys clock) * 20x (SERDES PLL) /10 (8/10 bit decoding)

Sys clock is same for both cases only PLLM value is different.

Hope this could help to you

Regards,

Albert