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AM625: A question about Audio sampling rate

Part Number: AM625

Hello,

There is an audio function block called McASP in the AM62 series of devices.
According to user manuals and reference manuals, it seems that it is possible to set and use sample rates such as 48kHz and 44.1kHz with audio protocols such as I2S from McASP. Is it possible to set and use sample rates such as 8kHz and 16kHz at lower rates?

Best regards,

K.Hirano

  • Hello Hirano, 

    Thank you for the query.

    We currently support 25 M crustal or oscillator.

    For 48 kHz, the oscillator frequency would need to be 24 MHz. The closest frequency achievable with a 25 MHz oscillator is 0.000000016% faster than 48 kHz.

    refer below sections in the TRM 

    12.1.1 Multichannel Audio Serial Port (MCASP)
    This section describes the Multichannel Audio Serial Port (MCASP).

    Figure 12-13. Receive Clock Generator Block Diagram

    Figure 12-12. Transmit Clock Generator Block Diagram

    Regards,

    Sreenivasa

  • Sreenivasa,

    Thank you for your responses.

    However, my customer would like to get 8KHz or 16KHz sample rate, not 48KHz.
    Is it possible to set 8KHz or 16KHz sample rete with 24MHz x-tal oscillator?

    Best regards,

    K.Hirano

  • Hello Hirano, 

    Thank you for the note.

    As mentioned above 24M crystal is currently not supported.

    Refer below section of the data sheet.

    7.11.4.1.1 MCU_OSC0 Internal Oscillator Clock Source

    Regards,

    Sreenivasa

  • Sreenivasa,

    With 25MHz crystal, is it possible to set lower rate like about 8KHz or 16KHz?

    Best regards,

    K.Hirano 

  • Hello Hirano, 

    Thank you for the note.

    I am checking on this.

    I assume you are checking if this is feasible and not tested.

    Regards,

    Sreenivasa

  • Sreenivasa,

    My customer would like to set about 8KHz or 16KHz sample rate somehow.
    I look forward to getting answer from you.

    Best regards,

    K.Hirano

  • Hello Hirano, 

    Thank you.

    Can you share the below clock requirements.

    Every McASP has a receive clocking section and a transmit clocking section. These are sometimes referred to as the receive port and the transmit port, and each clock port constitutes a clock zone. Therefore, each McASP has two potential clock zones. These can be run asynchronously with respect to each other, but in some cases, synchronous operation is appropriate.

    • AHCLKX and AHCLKR – These are high-frequency clocks pins, sometimes referred to as master clocks (often referred to on audio codecs as MCLK). McASP uses a master clock for one purpose: to divide it down and generate a bit clock. There are several cases where a master clock is not required.

    • ACLKX and ACLKR – These are bit clocks, often referred to on audio devices as BCK. Data is clocked in and out with respect to bit clock edges. Furthermore, much of McASP’s internal logic (state machines, and so forth) runs off of the bit clock, so a bit clock is ALWAYS required.

    • AFSX and AFSR – These are the frame sync clocks, often referred to as word clocks, or more commonly as left-right clocks (LRCK). The “left-right” terminology comes from stereo audio in the I2S format, in which the edges of the frame sync clock denote the bits corresponding to the left and right channels. The frame sync clocks run at the audio stream’s sample rate.

    Regards,

    Sreenivasa

  • Sreenivasa,

    Thank you for your additional explanations.
    However, since I am an analog oriented FAE, I do not understand well how I should respond to my customer's question.
    My customer's question is if they can set about 8KHz or 16KHz sample rate somehow.
    If you could respond with either "yes" or "No" first, it would be very nice.
    If your answer is "Yes", then let them know how.

    Best regards,

    K.Hirano

  • Hello Hirano, 

    Thank you.

    Since the required is to check the feasibility to generate 8KHz or 16KHz sampling clock, i went ahead with the below analysis:

    Refer the CTT - there is a provision for 100 M or 96 M  clock input to be selected a aux clk. 

    With 25 M crystal, the 100 M output is as below

    PLL2_hsdiv8 100 MHz

    With 100 M clock setting the 8KHz or 16KHz sampling rate should be possible. This is based on the CTT analysis and i am not sure if this has been verified or tested.

    Refer below the CTT snap shot

    In case 96 M clock is required to be used

    With 25 M crystal, the 96 M output is as below

    PLL1_hsdiv6

    95.99999994039536 MHz

    For 16 KHz the below can be achieved 

    15,999.999

    For 8 KHz the below can be achieved 

    7,999.99991

    Regards,

    Sreenivasa

  • Sreenivasa,

    Thanks a lot!

    Best regards,

    K.Hirano

  • Hello Hirano, 

    Thank you for the note.

    Regards,

    Sreenivasa