Hello Sai sirisha.

Thank you for the query.

Assuming you are new to AmM25 i have the following pointers 

Table 5-1. Device Comparison

Captures the availability of CPSWW3G.

6.3.1 CPSW3G
6.3.1.1 MAIN Domain

This section describes the external interface signals for CPSW3G.

RGMII

Table 6-2. CPSW3G0 RGMII1 Signal Descriptions

Table 6-3. CPSW3G0 RGMII2 Signal Descriptions

RMII

Table 6-4. CPSW3G0 RMII1 Signal Descriptions

Table 6-5. CPSW3G0 RMII2 Signal Descriptions

TRM 

12.3.1 Gigabit Ethernet Switch (CPSW3G)
This chapter describes the Gigabit Ethernet Switch (CPSW3G) subsystem in the device

12.3.1.2 CPSW0 Environment 

provide the connection of the RMII and RGMII interface with the EPHY

Figure 12-428. CPSW Top Level Block Diagram
12.3.1.4.2 CPSW Ports
The Ethernet Subsystem has three ports. Port 0 is the Host port (internal to the Subsystem). Port 1 and 2 are the external ports connected to RGMII, RMII, MII interfaces as per the interface selected.
Naming conventions followed in this chapter:
• Port0 is referred to the CPPI Host Port
• Port1 and 2 are referred to the interfaces RGMII/RMII/MII

Sirisha Chennamsetti said:

One is PHY and another is AM62x processor. In this AM62x processor, we have CPSW,ALE and CPPI blocks in hardware itself. Combination of all these blocks will be called as "CPSW_3G".

The interface section internal to the SoC is the CPSW3G and does not include the EPHY (Ethernet transceiver)

The EPHY interfaces to the SoC through CPSW3G.

I guess this helps you understand the AM625 CPSW better.

Please read through the TRM for CPSW related information to understand more with the CPSW3G capabilities.

Regards,

Sreenivasa

Hello Sai sirisha.

Could you please edit the tiltle of the thread as below. This help wider E2E users looking for CPSW3G information.

PROCESSOR-SDK-AM62X: ti am62x CPSW3G

Thank you for the help.

Regards,

Sreenivasa

Hi,

I got some clarity on am62x with the previous reply that i got from you. Thanks for that. As i was new to am62x, i need few clarifications on that. I am using AM62x SKEVM PROC114E3 hardware. Can you now please give me clarity on the below:

As per my understanding, AM62x soc is a chip in the "AM62x SKEVM PROC114E3" board and CPSW_3G is a block internal to that AM62x_SOC chip. And one EPHY chip will be connected to AM62x_SOC through RGMII and this is a chip that was mounted separately on the "AM62x SKEVM PROC114E3" board. 

1. Whether the AM62x_SOC is the whole "AM62x SKEVM PROC114E3" board or a single chip in that board?

2. Is CPSW_3G a separate chip or part of AM62x soc if AM62x_SOC is a chip?

3. Is CPSW_3G a separate chip in the "AM62x SKEVM PROC114E3" board if AM62x_SOC means the whole board? and where that CPSW_3G chip will be in the schematic if it is?

4. Please provide me the document with diagramatic representation if you can which should give clarity for me on this.

Thanks,

Ch. sai sirisha.

Hello Sai sirisha.

Thank you for the query.

You need to look at the block diagram in the datasheet and TRM  to understand the SoC peripherals. The CPSW is an ethernet peripheral internal to the SoC.

Please download the EVM and open the PDF schematics to understand the content of the EVM - SoC mounted on a board along with attached devices is an EVM.

The documents to refer are the datasheet, TRM and many other collaterals on TI.com.

Regards,

Sreenivasa