AM6442: DDRSS Timing specification

Biehler Aymeric

Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

Hi TI team,

I’m looking for timing specification of the DDRSS of the AM6442. I need some specific timing of your DDR controller in order to check by simulation that integrity and timings are ok.

Would you be able to give me those values :

Controller AM6442 Setting (Write) applies to Data and AddCmd Timing Parameters :
1. Minimum Transmit setup time : This is the minimum amount of setup time that is guaranteed to exist between the signals and their timing reference at the driving component, that is, the Controller.
2. Minimum Transmit hold time : This is the minimum amount of hold time that is guaranteed to exist between the signals and their timing reference at the driving component, that is, the Controller.

Controller AM6442 Setting (Read) Data Timing Parameters :
1. Max Receive Skew (+) : This is the maximum amount by which the Data is allowed to lag the Strobe at the receiving component, that is, the Controller.
2. Max Receive Skew (+) : This is the maximum amount by which the Data is allowed to lead the Strobe at the receiving component, that is, the Controller.

Those parameters are mandatory to validate the interface between LPDDR4 and AM64 by simulation.

Thank you

Best Regards

over 2 years ago

0 Christopher Roberts over 2 years ago

TI__Genius 9650 points

Aymeric,

Our functional expert is currently out of office so please expect a delay in response.

I do not believe timing parameters are provided for the DDR interface, instead we try and support successful design via the DDR Board Design and Layout app note. Have you been able to review this information?

Thanks,

Chris

0 Biehler Aymeric over 2 years ago in reply to Christopher Roberts

Prodigy 80 points

Christopher,

Totally understanding your point. We followed the DDR Board Design and Layout. TOday we made simulation of the interface between Controller and memory. As you know we are facing multisourcing on LPDDR4 which depending on provider have different timings. We just want to make that in any case we have enough timing margin to sustain reliability.

Best Regard

0 Lucas Bowe over 2 years ago in reply to Biehler Aymeric

TI__Expert 5875 points

Greetings Biehler,

As long as the app note is followed you should have plenty of margin by design, and for differing DDR vendors you can find our sysconfig tool to generate DDR configs. https://dev.ti.com/sysconfig/#/start

Sincerely,

Lucas

0 Biehler Aymeric over 2 years ago in reply to Lucas Bowe

Prodigy 80 points

Hi Lucas,

Agree with that but customer waiting from us a first validation level coming from simulation results. For that I need those timings. Would it be possible to get those or give me the IP model, I will ask to IP vendor those parameters.

0 Lucas Bowe over 2 years ago in reply to Biehler Aymeric

TI__Expert 5875 points

Greetings Biehler,

I don't think that's quite true about needing these timings, setup/hold + skew can be used for timing analysis with datasheet parameters, but DDR is not usually done in that simple of analysis.

DDR usually requires more involved simulations, an example of the methodology can be found in the AM62A DDR design guidelines Section 3: https://www.ti.com/lit/an/sprad66/sprad66.pdf

Resources for AM64 simulation: https://www.ti.com/product/AM6442#design-tools-simulation

Sincerely,

Lucas

0 Biehler Aymeric over 2 years ago in reply to Lucas Bowe

Prodigy 80 points

Hi Lucas,

Why TI do not provide those timings ? Are you not able to provide it because you don't have any property on the IP ?

0 Lucas Bowe over 2 years ago in reply to Biehler Aymeric

TI__Expert 5875 points

Greetings Biehler,

Signal integrity simulations (like data eyes) are critical with high speed signals, so we provide all the information (eye masks and IBIS models) required for those simulations. This with the DDR Board Design and Layout app note should ensure proper operation.

We support JEDEC standardized memories, so if the customer is dead set on finding some timing parameters they can reference the JEDEC standards JESD209-4 (LPDDR4) and JESD79-4 (DDR4). Note that these only describe the memory properties and not the properties of our controller, but they may be able to use that information to compare to memories they have selected. Section 2.4 and 3.4 of the DDR Board Design and Layout mention the necessary requirements for any JEDEC compatible memories.

Sincerely,

Lucas

0 Biehler Aymeric over 2 years ago in reply to Lucas Bowe

Prodigy 80 points

Clearly understand the point and associated timings from memories. Id' like to get same timing specification of the DDR Controller of TI AM64.

Would it be possible to get it or not ?

0 Lucas Bowe over 2 years ago in reply to Biehler Aymeric

TI__Expert 5875 points

Greetings Biehler,

We do not support that so unfortunately not.

Sincerely,

Lucas

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AM6442: DDRSS Timing specification