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How to interface C6670 with FPGA?

Other Parts Discussed in Thread: TMS320C6670

Hello!

As C6416 becomes obsolete part I am considering modern chip for future platform. Communications oriented C6670 with its coprocessors looks as good candidate. But I'm in a doubt about the following. On our current platform the jobs, which could not be complete in realtime are offloaded to FPGA and usually FPGA is lowest point in a chain between baseband processing and DAC/ADC. We used EMIF A of C6416 as Asynchronous Memory Interface. Also EMIF's were used for onboard CPLD chip access, USB and TCP/IP hardware accelerator. In C6670 spec I found, it has only one EMIF, designed for DDR3. What is suggested way to interface C6670 with external memory-like devices?

Thanks in advance.

  • As you mentioned the C6670 only has one EMIF.  For interfacing to an FPGA, I'd recommend SRIO or PCIe.  They can be setup for seamless operation of automated transfers and also have the flexibility of performing more misc. accesses.

    Best Regards,

    Chad

  • Thanks for the info. I suspected, that my knowledge obsolete too.

    Could you please give some more comments about PCIe versus SRIO? One thing I have discovered so far is that Xilix charge serious money for SRIO IP Core, while PCIe provided with ISE.

  • I have TMDSEVM6670LE board (TMS320C6670 with XDS560v2),  I want use it with FPGA board. Is there a recommended type of  FPGA board? FPGA board that has been proven to work with TMDSEVM6670LE board?

    Thank you,

    Mulyanto

  • The question posed is very broad and we should narrow down the focus a bit to see what you really need/want.

    Is there a particular IP(s) you'd prefer to interface between the FPGA and the DSP?

    What type of bandwidth do you require?

    Are there FPGA boards out there that are going to be able to directly interface to the C6670 EVM?

    The major FPGA vendors out there should have IP's available to support communication between our primary IO's and the FPGA.  PCIe, SRIO, GigE, I2C, SPI, UART, GPIO, etc.

    High speed SerDes interfaces such as PCIe, SRIO, SGMII of the GigE are going to require FPGA's with IO's that can support the high speed SerDes links and also will probably cost a bit extra for the IO Libraries.  It's best to work with the vendors to find out what these charges may be.  While the slower speed IO's such as I2C, SPI, UART, GPIO are not going to have this.

    As for FPGA Board that can directly interface to the EVM for this support, that may be more of a challenge as not too many vendors are necessarily building to work with our EVMs.  You may need to build some prototype boards for yourself with the FPGA on it.  Most IO's are coming out to headers in order to support such development.

    Best Regards,

    Chad

  • Hi Chad,

    you are right, I forgot to mention the bandwidth required.  I need about 100 Mbps interface, but I can't use the ethernet because its too fit. I avoid to use a custom fpga/interface (build by me) for my first prototype. I need a guaranteed interface. We have a lot altera and xilinx board and I always get problem in a custom interface (noise etc). So, instead of making my own fpga board/interface, I prefer to buy the appropriate board. Maybe a fpga board with SerDes(using the same Hyperlink cable)?

    Best Regards,

    Mulyanto



  • If you OK to proceed with Kintex, I've heard there will IP core for Hyperlink released soon. But I'm not sure, whether evaluation board does have appropriate connection. Other two options are Rapid IO and PCIe. Former one requires IP core priced by Xilinx with four digits. PCIe is available for free. Some affordable boards available with lower grade FPGAs, like Spartan 6 in LXT series. I plan to try this combination when all components arrive (don't you forget to order AMC to PCIe adaptor for your EVM?). If you get that faster, please share experience.

  • There was an announcement regarding the FPGA Source for support of HyperLink in FPGA by Integre Tek, which I posted yesterday on the Announcement tab

    That said, HyperLink (up to 50gbps) would be more than overkill for the 100mbps data.  I'm not sure of the pricing but I'd assume the Kintex w/ the faster IO's would be much higher in price than ones that would support PCIe which while still a bit overkill should be adequate for the needs.  And I would assume you could find off the shelf PCIe FPGA cards that you could use an Adaptor card to connect over PCI from the EVM's AMC header to PCIe interface such as TMDXEVMPCI 

    Best Regards,

    Chad