DSP BIOS HWI on DM6437

Saira

Other Parts Discussed in Thread: OMAP-L138

I am using DSP/ BIOS on DM6437 to use interrupt vector # 5 to map UART0 event 84. I configure HWI settings from HWI manager and disable GPIO interrupt to avoid shared interrupts on interrupt vector 5.

When I run the program with a break point in my ISR. The control transfers to the ISR only for once and does not enter in it again....Why this is so ??

Saira

over 14 years ago

0 Brad Griffis over 14 years ago

TI__Guru*** 125430 points

If you're only getting it once then most likely you have not properly cleared out one of the pending, enabled interrupts. See Table 11 "Interrupt Identification and Interrupt Clearing Information" in the UART Reference Guide for more details.

0 Saira over 14 years ago in reply to Brad Griffis

Intellectual 565 points

I have disabled the FIFO mode for the UART and now control enters the ISR 49 times and after that ISR is not invoked.........

From HWI manager I have set Interrupt # 5 as:

interrupt selection number : 84

function: _my_ISR

Use Dispatcher: true

Args: 0x0000000

Interrupt Mask: all

But still it is not going to run properly.

GPIO interrupts are also disabled.

What should I do next ????

0 Brad Griffis over 14 years ago in reply to Saira

TI__Guru*** 125430 points

Perhaps have a look at the UART examples for OMAP-L138 here:

http://processors.wiki.ti.com/index.php/QuickStartOMAPL1x_rCSL

The OMAP-L138 has the same UART peripheral as DM6437. In particular you should be careful with performing read-modify-write operations on the registers. Notice in the register map that some of the registers are mapped to the same address, i.e. a read of the address returns the contents of one register while a write will actually go to a different register. That's a fairly common mistake for people writing their own code.

0 Saira over 14 years ago in reply to Brad Griffis

Intellectual 565 points

Thanks alot... my ISR is working well...

but now I want to capture and display video in parallel with UART data reception... I map UART to HWI # 5 and capture and display video in DSP/BIOS TASK0. Control most of the time remains in UART ISR because it is of higher priority than Task0 function. I am not able to display video properly. Most of the time ISR is invoked and video capture buffers are not even initialized properly. UART is running on 19200 baud rate...

How this problem can be solved ???? How do the scheduling be performed so that both of the tasks work properly ??

0 Brad Griffis over 14 years ago in reply to Saira

TI__Guru*** 125430 points

Saira said:
Control most of the time remains in UART ISR because it is of higher priority than Task0 function.

Most of the time? What is it that you're doing in your ISR that is taking so long? Have you re-enabled the FIFO? If not, I highly recommend doing so in order to reduce the number of interrupts. You're not polling anywhere are you? A 19.2 kHz baud rate is very slow for a 600 MHz DSP, so there should be absolutely no reason why this interrupt should make any difference in the video performance.

0 Saira over 14 years ago in reply to Brad Griffis

Intellectual 565 points

In the ISR I make a packet of 25 bytes with a known header and than extract some of its fields....whenever the 4 byte header received , the subsequent incoming bytes start accumulating in a packet.

I didn't re-enable the FIFO because by enabling FIFO ISR is called only for once and the control didn't enter the ISR again.....what should be done to make it run well with FIFO mode ? May be the trigger level is to be set again....if yes than what it should it be for the said 19.2 kHz baud rate...?

I am not polling anywhere in the ISR....... in TSK function while loop is used to continuously capture and display video frames but it is not executing the TSK function well...

0 Brad Griffis over 14 years ago in reply to Saira

TI__Guru*** 125430 points

What did you change to get around the issue of the ISR being called 49 times? Could that change be related to why it wasn't working in FIFO mode?

Whether we are using the FIFO or not this should still be a trivial amount of processing. I think something more fundamental must be wrong. A couple ideas:

Have you enabled optimization in the compiler options to speed up your code? If you are right at the edge of real time then adding this tiny amount of UART HWI might break things.
Please verify your memory settings are correct (especially MAR bits) as described in this article: http://processors.wiki.ti.com/index.php?title=Enabling_64x%2B_Cache.

Best regards,
Brad

0 Saira over 14 years ago in reply to Brad Griffis

Intellectual 565 points

For resolving 49 times problem of that ISR I had disabled the FIFO mode by setting UART registers IER and IIR. In IER I enable Receiver Data Enable interrupt and disable ELSI (Receiver Line Status Interrupt) and ETBEI (Transmitter Holding Register Empty Interrupt) by setting IER value to 0x00000001............ In IIR I disable FIFO mode and set interrupt type to Receiver Data Available by setting its value to 0x00000004..... These setting are done at the time of UART initialization after setting Baud Rate etc...

For the cache coherency I use dynamic configuration...

When I enable the FIFO mode ...FIFO overflow error occurs.... I read the RBR register as:

CSL_UartRegsOvly uartModuleRegs = (CSL_UartRegsOvly)(0x01C20000u);

void my_ISR()

{

Uint8 buffer[8];

*buffer = uartModuleRegs->RBR;

ch = (char)(buffer[0]);

}

What should I do to read the RBR in FIFO mode ??

0 Brad Griffis over 14 years ago in reply to Saira

TI__Guru*** 125430 points

Saira said:
In IIR I disable FIFO mode and set interrupt type to Receiver Data Available by setting its value to 0x00000004.....

You are making a severe mistake here. I previously warned you about this. IIR is a READ ONLY register. You cannot write to it. At the same address is the FCR, so when you think you are writing to IIR you are in fact writing to FCR. Writing 0x4 to FCR simply clears the transmit FIFO. Furthermore, the description of DMAMODE1 says "Always write 1 to DMAMODE1" which you are not doing.

You should write to FCR such that DMAMODE1=1, RXFIFTL=2 (8 bytes), and FIFOEN=1. Do NOT perform a read-modify-write. It must be a straight-up write or else you'll be reading IIR.

0 Saira over 14 years ago in reply to Brad Griffis

Intellectual 565 points

ohhhh Thanx... I have updated the code...now FCR is written by the value 0x8D with DMAMODE1 = 1, TXCLR =1, RXCLR =0, RXFIFTL = 2 (8 bytes) and FIFOEN = 0...it works well..the ISR is called for every interrupt but when I set FIFOEN bit than the previous problem of calling ISR only for once arises. This is due the an error that is Receive Line error - FIFO Overflows......

Is this because I m reading the RBR register only for once by

*buffer = uartModuleRegs->RBR;

Regards

Saira

0 Brad Griffis over 14 years ago in reply to Saira

TI__Guru*** 125430 points

Saira said:

when I set FIFOEN bit than the previous problem of calling ISR only for once arises. This is due the an error that is Receive Line error - FIFO Overflows......

Is this because I m reading the RBR register only for once by

*buffer = uartModuleRegs->RBR;

Yes, I would write create a loop such as

while ( (uartModuleRegs->LSR & 1) == 1 ) // data still in FIFO

{

*buffer++ = uartModuleRegs->RBR;

}

0 Saira over 14 years ago in reply to Brad Griffis

Intellectual 565 points

I have done it by clearing receiver FIFO at the time of initialization...Thanks alot

I want to see the count of Task function and ISR in Statistics View. I can see the ISR information but task information is not displayed......How it can be done ?

0 Brad Griffis over 14 years ago in reply to Saira

TI__Guru*** 125430 points

http://processors.wiki.ti.com/index.php/Guidelines_for_Posting_on_the_E2E_Forums#Only_one_problem.2Fquestion_per_post.21

Processors

Processors forum

DSP BIOS HWI on DM6437