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TDA4AH-Q1: Interrupt Aggregator CSL-layer functions functions don't work on A72 & R5F

Scott Brown
Prodigy 190 points
Part Number: TDA4AH-Q1
Other Parts Discussed in Thread: TDA4VM

Hello TI,

I have been testing out some custom code on both the MCU R5F (core0) & A72 (cluster0_core0) using some of the PDK functions from the CSL layer on the J784S4 EVM board.

I started up by modifying the example for the Mailboxes already present in the PDK (to keep the compile chain) and adding some code to route an interrupt from the mailbox cluster towards the GIC500, using the UDMA Interrupt Aggregator & Router.

Using the CSL layer, I have tried to correctly configure the Interrupt Aggregator (following the Interrupt Configuration process from the section 10.2.1.3 of the TDA4AH TRM) from the A72 but to no avail.

I can successfully configure the LEVI2GEVI.MAP register (i.e. I can R/W the register) but both the GEVI.IMAP & INTR.VINTR.ENABLE_SET or ENABLE_CLEAR are readable but never writable when using CSL-FL CSL_intAggr functions (addresses are correct, MMU region is accessible and PHYS==VIRT).

Have I missed something important that prevents me from writing into those registers ? I must add that my data structure in correctly configured using the CSL_IntaggrCfg struct.

Thank you for your time and your answer.

  • 0
    TI__Guru**** 476905 points

    Hi Scott Brown,

    Please SciClient interface to configuring interrupt router. It is not recommended to use direct registers access for these modules.

    Regards,

    Brijesh 

  • 0 in reply to Brijesh Jadav
    Prodigy 190 points

    Hi, Thanks for your answer, but I am working with the Interrupt Aggregator, not the Interrupt Router. I have some follow-up questions :

    • Where then can I find additional information on the correct configuration process of this peripheral using the SciClient ?
    • For the same peripheral in the TDA4VM TRM package, the register documents mentions a cfg_rsel signal : what is that signal ? How is it used/addressed ? I couldn't find any other mention of it in any document except from the registers.

    Thanks again for your time

  • 0 in reply to Scott Brown
    TI__Guru**** 476905 points

    Hi Scott,

    Many of these registers will not be available once we load TIFS on the M3/M4 core and run Sciserver on mcu1_0 core. It is then recommended to use SciClient interface for setting up Interrupt routers and aggregators.

    Which Interrupt Aggregator would you like to configure? Could you please share some information?

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 190 points

    Hi,
    Thanks a lot for your answer.

    I'm interested in setting up a local Mailbox event (LEVI) as a GEVI in the NavSS0 Main, so make it go through the NAVSS0_INTR0_INTR_AGGR, the NAVSS0_INTR0_INTR_ROUTER and towards the GIC500 for A72_0_0 to service the IRQ.

    - Should I then use the Sciclient_rmIrqSet() drv function to implement the desired result ?
    - Can I just modify the SBL/SciClient init routines to setup my interrupts through direct register access ?

    Thanks in advance for your time once again.

  • 0 in reply to Scott Brown
    TI__Guru**** 476905 points

    Hi Scott,

    Do you mean to first the L2G register? This register should be accessible.. Regarding Interrupt Aggregator and Router, the only module which configures/supports them is UDMA. UDMA internally uses/configures both of them to get the channel interrupts.. I would suggest to refer to the UDMA driver for configuring them.

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 190 points

    Hi Brijesh,

    Yes, I want to use the L2G register to map the CSLR_NAVSS0_UDMASS_INTA_0_INTAGGR_LEVI_PEND_NAVSS0_MAILBOX_0_PEND_INTR_0 source interrupt of NAVSS0_UDMASS_INTA_0 to the GEVI index 56 (not setup in the SDK, meaning I'm trying to do the config from scratch), output it as VINTR index 100, send it inside the interrupt router and output it to CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_100 (input pin 484) of the GIC500.

    Is it the Sciclient or the UDMA driver to use then ? I'm confused as per your answers.

    Thanks in advance for your time and response.

  • 0 in reply to Scott Brown
    TI__Guru**** 476905 points

    Unlocking this ticket.

    Are you still seeing this issue? Can you please update the status?

    Regards,

    Brijesh