I found a limitation in the incoming pixel clock. It is around 78MHz when running SDRAM on 166/322 MHz and around 97MHz when running on 200/400MHz. (sensorchip is master of clock).
As far as I found the ISP/CAM block capability is depending on L3-ICLK, but this is the same as for DRAM. So this is my real limit. In datasheet I found that pixelclock of 120MHz is supported (8Bit images). How is this working? Is this only possible, if the clock is sourced by OMAP?
Best regards
