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AM5718: AM5718

Long Nguyen
Prodigy 20 points

Part Number: AM5718

Hello,

I have a board design with a Sitara Processor (Part Number: AM5718AABCXA) and two identical 10/100/1000 Ethernet PHYs (Part Number: DP83867ISRGZ). Both PHYs are connected to the Sitara Processor via RGMII Interfaces (RGMII0 and RGMII1). Pin Mux Tool is used to configure the pins of the Sitara Processor for RGMII1 Interface properly. At power-up, the Sitara Processor and both PHYs come up with both PHYs auto-negotiate at 1000 when both are connected to a 1G Switch. I am able to send and receive Ethernet Packets with the first PHY (PHY 0) but I am not able to send or receive any Ethernet Packet with the second PHY (PHY 1).

Oscilloscope captures show that the Sitara Processor outputs RGMII0_TXC correctly (2.5MHz for 10; 25MHz for 100; 125MHz for 1000 Speed) so PHY 0 is working. However, Oscilloscope captures reveal that there is no clock coming out of RGMII1_TXC Pin (Ball Number D5) so PHY 1 is not working.

1. Is there any register/bit setting(s) I need to do in side the Sitara Processor to enable the Sitara Processor to output the clock for RGMII1_TXC to PHY 1?

2. Can you provide some recommendations to allow me to determine why the Sitara Processor does not drive its RGMII1_TXC pin with RGMII Transmit Clock?

3. Looking at the U-Boot mux_data.h file for the am571x_idk Evaluation Board, I notice a line

   {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},      /* vin2a_d12.rgmii1_txc */

   which indicates that Ball Name VIN2A_D12 (Ball Number D5) is set to to Mode 3 using Pin Mux Tool so this Ball functions as RGMII1_TXC. The Sitara

   Datasheets also indicates that RGMII1_TXC is an Output Pin which does not match PIN_INPUT_PULLDOWN shown in the line above (I also see the same thing     for other pins that are related to RGMII1 TX group).

   Should this Ball Name VIN2A_D12 (and other Ball Names that belong to RGMII1 TX group) be PIN_OUTPUT instead of PIN_INPUT_PULLDOWN because all

   RGMII1 TX Pins are Output Pins from the Sitara Processor?

4. For my customized mux_data.h file, I have

   {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)},      /* vin2a_d12.rgmii1_txc */

   instead (Same for other pins in RGMII1 TX group). Could this be the cause of the Sitara Processor not driving RGMII1 TXC with a proper clock?

Thank you very much for your support.

Regard,

Long Nguyen

Long.Thanh.Nguyen@lmco.com

856-722-7277

  • 0
    TI__Mastermind 38790 points

    Hi,

    Are you using ethernet from linux or is it a RTOS application which is controlling ethernet?

    A recommendation from my side would be to try a MAC loopback test once. The loopback bit can be controlled by bit 1 of SL_MACCONTROL register for slave2. You can set this bit and try to send packets out. See if you can receive these packets from the CPSW statistics.

    Regards,
    Tanmay