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PROCESSOR-SDK-AM62X: How to test SRAM and ROM using PBIST in TI SDK 08.06?

Long Nguyen
Prodigy 40 points
Part Number: PROCESSOR-SDK-AM62X

Currently, in the MCU_PLUS_SDK 08.06 version, I have not found specific support for PBIST to test SRAM and ROM.It seems that the available PBIST options in the SDK 08.06 include GPU PBIST, SDL_PBIST_INST_MPU, MAIN_PBIST, and DM_PBIST, but there is no explicit mention of SRAM and ROM testing.

I want to inquire whether the current version of MCU_PLUS_SDK 08.06 supports PBIST for testing SRAM and ROM. If it does, what should be done?

Thanks,

Long Nguyen

  • 0
    TI__Mastermind 20516 points

    Hello,

    PBIST test for ROM is not supported for AM62x and is not currently on the roadmap. 

    You can call the PBIST self-test API provided in MCU+SDK and that will test all the supported memory regions including the SRAM region.

    Regards,

    Nihar Potturu.  

  • 0 in reply to Nihar Potturu
    Prodigy 20 points

    Hi ,

    Regarding PBIST test for SRAM, there was no documentation in details of which macros are suitable to enable when we look at the SDK example.

    Below is how we implement it (DM PBIST is using):

    - SRAM for R5F, we are using below macros:

    #define SDL_WKUP_R5FSS0_CORE0_ICACHE_BASE                                                          (0x74000000UL)
#define SDL_WKUP_R5FSS0_CORE0_ICACHE_SIZE                                                          (0x800000UL)
#define SDL_WKUP_R5FSS0_CORE0_DCACHE_BASE                                                          (0x74800000UL)
#define SDL_WKUP_R5FSS0_CORE0_DCACHE_SIZE                                                          (0x800000UL)
#define SDL_WKUP_R5FSS0_CORE0_ATCM_BASE                                                            (0x78000000UL)
#define SDL_WKUP_R5FSS0_CORE0_ATCM_SIZE                                                            (0x8000UL)
#define SDL_WKUP_R5FSS0_CORE0_BTCM_BASE                                                            (0x78100000UL)
#define SDL_WKUP_R5FSS0_CORE0_BTCM_SIZE                                                            (0x8000UL)

    - SRAM for SMS, we are using below macros:

    #define SDL_SMS0_HSM_SRAM0_0_BASE                                                                  (0x43c00000UL)
#define SDL_SMS0_HSM_SRAM0_0_SIZE                                                                  (0x20000UL)
#define SDL_SMS0_HSM_SRAM0_1_BASE                                                                  (0x43c20000UL)
#define SDL_SMS0_HSM_SRAM0_1_SIZE                                                                  (0x10000UL)
#define SDL_SMS0_HSM_SRAM1_BASE                                                                    (0x43c30000UL)
#define SDL_SMS0_HSM_SRAM1_SIZE                                                                    (0x10000UL)
#define SDL_SMS0_TIFS_SRAM0_BASE                                                                   (0x44040000UL)
#define SDL_SMS0_TIFS_SRAM0_SIZE                                                                   (0x20000UL)
#define SDL_SMS0_TIFS_SRAM1_0_BASE                                                                 (0x44060000UL)
#define SDL_SMS0_TIFS_SRAM1_0_SIZE                                                                 (0x8000UL)
#define SDL_SMS0_TIFS_SRAM1_1_BASE                                                                 (0x44068000UL)
#define SDL_SMS0_TIFS_SRAM1_1_SIZE

    Questions:

    1. Are these correct macros to enable? 

    2. Are these sufficient for SRAM of R5F and SMS?

    Thank you very much.