C6720 SPI Control Registers - word writes

dan kantorski

I have an application where I need to write 20 bits through the serial port using the SCS line as a sync. The SPI port has a max bit transfer of 16 Originally, I was planning to manually control the SCS line as a GPIO asserting before writing and desserting it after the two transfers one 16 bit and one 4 bit. I saw that in the SPIDAT1 register, there is a CS hold. So, I can setup the word format registers to the 2 required formats, send the two transfers calling on those formats and keep the CS control asserted between each. Looking into the SPRU718B manual Pg 49 and 50. There is a caution on Pg 50 regarding how to operate this feature to prevent a glitch.

The question: when a register is classified as a word read/write, is the term "word" considered to be 16 bits or 32 bits. If a word is considered 16 bits, I can offset the memory location as base +2 or 4700_003E for SPIDAT1 and rewrite this bit using a short pointer to this location? If a word is considered 32 bits, how can this be done?

Thanks in advance for any help. Regards...

over 16 years ago

0 TimHarron over 16 years ago

TI__Mastermind 18130 points

The term 'word' is generally very ambiguous and its meaning often depends on the context in which it is used. For example, a 'word' on the C6000 processors typically refers to 32-bit data; however, in some peripherals a 'word' can be of variable lengths (see SPIFMTx in that same SPI manual). Where specifically did you see a register defined as a word read/write? There may surrounding context that can pin-point exactly what is meant.

*edit*

dan kantorski said:
The question: when a register is classified as a word read/write, is the term "word" considered to be 16 bits or 32 bits. If a word is considered 16 bits, I can offset the memory location as base +2 or 4700_003E for SPIDAT1 and rewrite this bit using a short pointer to this location? If a word is considered 32 bits, how can this be done?

After re-reading your question, are you asking whether or not a register can be accessed on a byte-boundary as opposed to the full 32-bit boundary? The 6000 architecture does allow for byte-level addressing, but I do not know if the registers will function properly (I've never tested this). If this is what you're after I can look into this further.

0 dan kantorski over 16 years ago in reply to TimHarron

Intellectual 910 points

The memory map summary table 2.7 out of the spr370E states that the SPI control registers are word addressable only.

For using the CSHOLD function in the SPIDAT1 register there is a caution noted regarding glitches that may be seen:

"When data is written to the SPIDAT1 register with the CSHOLD bit set to ‘1’,
the master keeps the SPIx_SCS asserted at the end of the transfer. When data
is written to the SPIDAT1 register with CSHOLD set to ‘0’ the master de asserts
the SPIx_SCS pin at the end of the transfer. However it is found that when
SPIx_SCS is asserted and data is written to the SPIDAT1 register with the
CSHOLD set to ‘0’ the SPIx_SCS gets momentarily deasserted and asserted
back resulting in a glitch.To avoid such a glitch all transfers during which
SPIx_SCS should be active the user should write to SPIDAT1 register with
CSHOLD set to ‘1’. This should be followed by a write to only the CSHOLD field
with a value ‘0’. Alternatively the user can write to the CSHOLD fields only
before and after the set of transfers to toggle the SPIx_SCS and write only to
the SPIDAT1[15:0] during the transfers."

Based on this statement am I to understand that this register may be byte addressable? This note almost leads me to believe it is bit addressable (i know this is not possible though)??

If I perform a write to the whole register or the lower bytes (if possible) this would start a transfer, correct? So, based on the caution, if I need to send 20 bits: I would write to the full register selecting the format register defining the first 16 bits with the CS hold high. I would perform another full register write selecting the format register of 4 bits, still keeping CSHOLD high to prevent the glitch. After the second transfer, I will need to release the CSHOLD bit so the DSP releases the SCS line for the latch on my external serial device. How to do this without initiating another transfer? An upper word write while performing the second transfer could be the answer.

Another question may be what constitutes a consecutive transfer. Is this a loose term just meaning "between transfers" or does it imply transfers done one immediately after the other. Meaning if I do not immediately execute another register write after the second transfer, will the SCS line be de asserted automatically without any further action or do I physically needs to change the CSHOLD bit.

I guess the real question is how to manipulate the register around the caution and get all 20 bits latched to my device. And yes if you could look further into accessing registers on a byte boundary (this ultimately is what I am after)

If all else fails, I can just configure the SCS line a GPIO and manually perform the operation as we had talked about a while back.

0 dan kantorski over 16 years ago in reply to TimHarron

Intellectual 910 points

I pressed ahead and just coded it. It seemed to work correctly.

I coded a variable:

unsigned short* const SPI1_DAT1UW=(unsigned short*)0x4800003E;

And the basics of the routine were:

a=control | 0x11000000;
    *SPI1_DAT1=a;

    do{
        a=*SPI1_BUF;
        a=a & 0x20000000;
    }while (a!=0);

    a=setpoint | 0x10000000;
    *SPI1_DAT1=a;

    for (a=10;a>0;a--)
        {
        asm("     NOP");
        }

    *SPI1_DAT1UW=0x0000;

    do{
        a=*SPI1_BUF;
        a=a & 0x20000000;
    }while (a!=0);

this kept the scs line low for the two transfers and changing just the top portion of the register after the second transfer started gave me the rise on the SCS line as soon as the second transfer completed. There is quite a gap between the consecutive transfers but it worked nevertheless.

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C6720 SPI Control Registers - word writes