Hello,
Everyone.I'm doing with Lyrtech's DVDP648.I want to use video port 3 to capture BT.656 576x704 interlaced video.I can receive Y
signal correctly,but can not receive Cb and Cr signal.I link the EDMA PaRam-Set to null-PaRam-Set when a frame is completed.I go
to see the EDMA registers window with CCS,I can find that only the Y-signal corresponding PaRam-Set is null-PaRam-Set ,but Cb
and Cr corresponding PaRam-Set don't link to null-PaRam-Set ,and I can find only 2 double words of Cb and Cr data have been
transfered from the DST entry of the OPT i of the corresponding PaRam-Set .And I can find there was no event missing from EMR and
EMRH regesters in EDMA.It implys that only two VPCbEVTA and VPCrEVTA event signal generated. I can also find the value of VPIS
register in VP3 is 0x00000006,and this implys video capture have completed and there was FIFO overruned. So it's complicated and
I can't find where the problem is.
the following is some setup parameters with video port and EDMA.
/***************************************** VIDEO PORT SETUP***************************************/
#define PORTPARAM {\
/* //以下通过VPCTL寄存器设置 */\
/* */\
/* //设置作为视频捕获还是视频显示，0：capture 1：display */\
0,/* */\
/* //双通道还是单通道，0：single channel 1：dual channel */\
0,/* //dual channel */\
/* //VPXCLK1极性是否翻转，只用于视频显示口 1：翻转 (inverse) */\
0,/* */\
/* //VPxCTL0,1, 2极性设置 0:高有效（active high） 1：低有效(active low) */\
0,0,0/* */\
}
/*********************************************CAPTURE PORT SETUP***************************************/
#define CAPPARAM {\
/* //VCACTL,VCBCTL */\
/* //capture mode select 0:8-bit BT.656 */\
/* // 2:8-bit raw */\
/* // 4:16-bit Y/C */\
/* // 6:16-bit raw */\
0,/* //Uint8 cmode; */\
/* //操作模式选择，CON,FRAME,CF2，CF1 */\
/* //1：Noncontinuous field 1 capture */\
/* //2：Noncontinuous field 2 capture */\
/* //3：Noncontinuous field 1 and field 2 capture */\
/* //4：Noncontinuous frame capture */\
/* //5：Noncontinuous progressive frame capture */\
/* //7：Single frame capture */\
/* //9:Continuous field 1 capture */\
/* //10:Continuous field 2 capture */\
/* //12:Continuous frame capture. */\
/* //13:Continuous progressive frame capture */\
7,/* //Uint8 cfcc;//CON,FRAME,CF2，CF1 */\
/* //scaling，0：no,1:1/2 scaling */\
0,/* //Uint8 scale; */\
/* //resampling，0：no 1:yes */\
0,/* //Uint8 resmpl; */\
/* //HCOUNT VCOUNT reset method,field detect method */\
1,0,0,/* //Uint8 hrst,vrst,fldd; */\
/* //选择用同步信号，还是EAV/SAV 0:用EAV、SAV 1：用同步信号 */\
0,/* //Uint8 exc; */\
/* //F位。。。0:Detected 0 is field 1. */\
/* // 1:Detected 0 is field 2. */\
1,/* //Uint8 finv; */\
/* */\
/* //VCxSTRT1,场1图像起始位置，x代表A或B */\
0,25,/* //Uint16 vcxstart1,vcystart1;//vcxstart必须是偶数 */\
/* */\
/* //VCxSTOP1,场1图像终止位置 */\
704,312,/* //Uint16 vcxstop1,vcystop1; */\
/* */\
/* //VCxSTRT2,场2图像起始位置，x代表A或B */\
0,26,/* //Uint16 vcxstart2,vcystart2;//vcxstart必须是偶数 */\
/* */\
/* //VCxSTOP2,场2图像终止位置 */\
704,313,/*860,313, //Uint16 vcxstop2,vcystop2; */\
/* */\
/* //VCxTHRLD,阈值 */\
88,88,/*88,88, //Uint16 vcthrld1,vcthrld2;//只有10位 */\
/* */\
/* //VCxEVTCT,设置每场的事件数 */\
288,288/* //Uint16 capevtct1,capevtct2; */\
}
/**************************************************Y PARAM-SET***********************************************/
#define EDMAPARAMY_FLD1 {\
/* //传输通道 */\
38,/* Uint8 chan; */\
/*//传输队列，也就是TC0~TC3,0的优先级最高，3的优先级最低 */\
1,/*Uint8 queue; */\
/* //传输所用参数集 */\
38,/* Uint16 paramsetnum; */\
/* //paramset */\
/* //opt */\
/* //Source/Destination address mode. */\
/* //0:Increment (INCR) mode */\
/* //1:Constant addressing (CONST) mode */\
0,/* 0,Uint8 sam; */\
0,/* Uint8 dam; */\
/* //传输同步方式,0:A-synchronized 1:AB-synchronized. */\
1,/*1, Uint8 syncdim; */\
/* //Static set.0:Set is not static 1: Set is static */\
0,/* Uint8 static_; */\
/* //FIFO Width 0:8-bit 1:16-bit 2:32-bit 3:64-bit 4:128-bit
*/\
/* //5:256-bit */\
0,/* 0, Uint8 fwid; */\
/* //Transfer complete code mode. */\
/* //0:Normal completion: A transfer is considered completed
*/\
/* //after the data has been transferred. */\
/* //1:Early completion: A transfer is considered completed after
*/\
/* //the EDMA3CC submits a TR */\
0,/* Uint8 tccmode; */\
/* //Transfer complete code.6位二进制,0-0x3F */\
38,/* Uint8 tcc; */\
/* //Transfer complete/Intermediate transfer completion interrupt
*/\
/* //enable. */\
/* //0:Transfer complete interrupt is disabled. */\
/* //1:Transfer complete interrupt is enabled. */\
0,/* Uint8 tcinten; */\
0,/* Uint8 itcinten; */\
/* //Transfer complete/Intermediate transfer completion chaining
*/\
/* //enable. */\
/* //0:Transfer complete chaining is disabled. */\
/* //1:Transfer complete chaining is enabled. */\
0,/* Uint8 tcchen; */\
0,/* Uint8 itccen; */\
/* //Channel Source Address (SRC) */\
CSL_VP3_CHANNELA_DATA,/* Uint32 src; */\
/* //Channel Destination Address (DST) */\
0,/* Uint32 dst; */\
/* //Count for 1st Dimension (ACNT) */\
8, /*704, Uint16 acnt; */\
/* //Count for 2nd Dimension (BCNT) */\
88, /*576, Uint16 bcnt; */\
/* //Count for 3rd Dimension (CCNT) */\
576,/*1, Uint16 ccnt; */\
/* //BCNT Reload (BCNTRLD) */\
0,/*576, Uint16 bcntrld; */\
/* //Source B Index (SRCBIDX) */\
0,/* Int16 srcbidx; */\
/* //Destination B Index (DSTBIDX) */\
8,/*704,1408, Int16 dstbidx; */\
/* //Source C Index (SRCCIDX) */\
0,/* Int16 srccidx; */\
/* //Destination C Index (DSTCIDX) */\
704,/* 0, Int16 dstcidx; */\
/* //Link Address (LINK),aligned 32-byte,The 5 LSBs of the LINK
*/\
/* //field should be cleared to 0. */\
/* //The EDMA3CC ignores the upper 2 bits of the LINK entry */\
0xffff/* (38+64)<<5 Int16 link;38+64 */\
}
/**************************************************Cb PARAM-SET***********************************************/
#define EDMAPARAMCb_FLD1 {\
/* //传输通道 */\
39,/* Uint8 chan; */\
/*//传输队列，也就是TC0~TC3,0的优先级最高，3的优先级最低 */\
0,/*Uint8 queue; */\
/* //传输所用参数集 */\
39,/* Uint16 paramsetnum; */\
/* //paramset */\
/* //opt */\
/* //Source/Destination address mode. */\
/* //0:Increment (INCR) mode */\
/* //1:Constant addressing (CONST) mode */\
0,/* Uint8 sam; */\
0,/* Uint8 dam; */\
/* //传输同步方式,0:A-synchronized 1:AB-synchronized. */\
0,/* Uint8 syncdim; */\
/* //Static set.0:Set is not static 1: Set is static */\
0,/* Uint8 static_; */\
/* //FIFO Width 0:8-bit 1:16-bit 2:32-bit 3:64-bit 4:128-bit
*/\
/* //5:256-bit */\
0,/* Uint8 fwid; */\
/* //Transfer complete code mode. */\
/* //0:Normal completion: A transfer is considered completed
*/\
/* //after the data has been transferred. */\
/* //1:Early completion: A transfer is considered completed after
*/\
/* //the EDMA3CC submits a TR */\
0,/* Uint8 tccmode; */\
/* //Transfer complete code.6位二进制,0-0x3F */\
39,/* Uint8 tcc; */\
/* //Transfer complete/Intermediate transfer completion interrupt
*/\
/* //enable. */\
/* //0:Transfer complete interrupt is disabled. */\
/* //1:Transfer complete interrupt is enabled. */\
0,/* Uint8 tcinten; */\
0,/* Uint8 itcinten; */\
/* //Transfer complete/Intermediate transfer completion chaining
*/\
/* //enable. */\
/* //0:Transfer complete chaining is disabled. */\
/* //1:Transfer complete chaining is enabled. */\
0,/* Uint8 tcchen; */\
0,/* Uint8 itccen; */\
/* //Channel Source Address (SRC) */\
CSL_VP3_CHANNELA_DATA+0x20,/* Uint32 src; */\
/* //Channel Destination Address (DST) */\
0,/* Uint32 dst; */\
/* //Count for 1st Dimension (ACNT) */\
8,/* Uint16 acnt; */\
/* //Count for 2nd Dimension (BCNT) */\
44,/*576, Uint16 bcnt; */\
/* //Count for 3rd Dimension (CCNT) */\
576,/*1, Uint16 ccnt; */\
/* //BCNT Reload (BCNTRLD) */\
0,/*576, Uint16 bcntrld; */\
/* //Source B Index (SRCBIDX) */\
0,/* Int16 srcbidx; */\
/* //Destination B Index (DSTBIDX) */\
8,/*352, 704 Int16 dstbidx; */\
/* //Source C Index (SRCCIDX) */\
0,/* Int16 srccidx; */\
/* //Destination C Index (DSTCIDX) */\
352,/*0, Int16 dstcidx; */\
/* //Link Address (LINK),aligned 32-byte,The 5 LSBs of the LINK
*/\
/* //field should be cleared to 0. */\
/* //The EDMA3CC ignores the upper 2 bits of the LINK entry */\
0xffff/*(39+64)<<5 Int16 link;39+64 */\
}
/**************************************************Cr PARAM-SET***********************************************/
#define EDMAPARAMCr_FLD1 {\
/* //传输通道 */\
40,/* Uint8 chan; */\
/*//传输队列，也就是TC0~TC3,0的优先级最高，3的优先级最低 */\
0,/*Uint8 queue; */\
/* //传输所用参数集 */\
40,/* Uint16 paramsetnum; */\
/* //paramset */\
/* //opt */\
/* //Source/Destination address mode. */\
/* //0:Increment (INCR) mode */\
/* //1:Constant addressing (CONST) mode */\
0,/* Uint8 sam; */\
0,/* Uint8 dam; */\
/* //传输同步方式,0:A-synchronized 1:AB-synchronized. */\
0,/* Uint8 syncdim; */\
/* //Static set.0:Set is not static 1: Set is static */\
0,/* Uint8 static_; */\
/* //FIFO Width 0:8-bit 1:16-bit 2:32-bit 3:64-bit 4:128-bit
*/\
/* //5:256-bit */\
0,/* Uint8 fwid; */\
/* //Transfer complete code mode. */\
/* //0:Normal completion: A transfer is considered completed
*/\
/* //after the data has been transferred. */\
/* //1:Early completion: A transfer is considered completed after
*/\
/* //the EDMA3CC submits a TR */\
0,/* Uint8 tccmode; */\
/* //Transfer complete code.6位二进制,0-0x3F */\
40,/* Uint8 tcc; */\
/* //Transfer complete/Intermediate transfer completion interrupt
*/\
/* //enable. */\
/* //0:Transfer complete interrupt is disabled. */\
/* //1:Transfer complete interrupt is enabled. */\
0,/* Uint8 tcinten; */\
0,/* Uint8 itcinten; */\
/* //Transfer complete/Intermediate transfer completion chaining
*/\
/* //enable. */\
/* //0:Transfer complete chaining is disabled. */\
/* //1:Transfer complete chaining is enabled. */\
0,/* Uint8 tcchen; */\
0,/* Uint8 itccen; */\
/* //Channel Source Address (SRC) */\
CSL_VP3_CHANNELA_DATA+0x40,/* Uint32 src; */\
/* //Channel Destination Address (DST) */\
0,/* Uint32 dst; */\
/* //Count for 1st Dimension (ACNT) */\
8,/*352, Uint16 acnt; */\
/* //Count for 2nd Dimension (BCNT) */\
44,/*576, Uint16 bcnt; */\
/* //Count for 3rd Dimension (CCNT) */\
576,/* Uint16 ccnt; */\
/* //BCNT Reload (BCNTRLD) */\
0,/*576, Uint16 bcntrld; */\
/* //Source B Index (SRCBIDX) */\
0,/* Int16 srcbidx; */\
/* //Destination B Index (DSTBIDX) */\
8,/*352, Int16 dstbidx; */\
/* //Source C Index (SRCCIDX) */\
0,/* Int16 srccidx; */\
/* //Destination C Index (DSTCIDX) */\
352,/*0, Int16 dstcidx; */\
/* //Link Address (LINK),aligned 32-byte,The 5 LSBs of the LINK
*/\
/* //field should be cleared to 0. */\
/* //The EDMA3CC ignores the upper 2 bits of the LINK entry */\
0xffff/*(40+64)<<5 Int16 link;40+64 */\
}