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AM6442: TCM access manner

Tsurumoto
Genius 16885 points

Part Number: AM6442

Hi Pekka,

The following are the general questions, so I moved them here, and will close the other E2E thread later.

Pekka Varis said:
All the internal and external memory is visible for all cores in the SoC memory map (see 2.1 MAIN Domain Memory Map in https://www.ti.com/lit/pdf/spruim2 ). The 2MB internal MSRAM is made up of 8 regions/banks each of size 256kB. If two cores access same region in the same clock cycle, one will stall for a few nanoseconds.
 

  

ATCM is listed at Table2-1 "MAIN Domain Memory Map" in https://www.ti.com/lit/ug/spruim2f/spruim2f.pdf as the below

    

then, all TCM memories can be access from all cores (i.e. A53, R5F, M4F) at HW point of view, I think.

But I'm worrying if the access to TCM is limited by SW.

  

1) Does AM64x some restriction to access to ATCM (because of ROM code)?

2) Is there other memory that have some access restriction by SW (e.g. ROM code, bootloader, or other SDK code).

3) Is R5FSS0_CORE0_ATCM accessible from R5FSS1_CORE1, right?

4) I think, R5FSS0_CORE0 uses the following direct path to access to R5FSS0_CORE0_ATCM.

     

  

     And, other cores (e.g. R5FSS0_CORE1 the following direct path to access to R5FSS0_CORE0_ATCM.

      

  

     Does it correct?

5) How about the access latency to

       - from R5FSS0_CORE0 to R5FSS0_CORE0_ATCM.

       - from R5FSS0_CORE1 to R5FSS0_CORE0_ATCM

       - from other cores (e.g. A53, M4F) to R5FSS0_CORE0_ATCM

  

6)  How to priories each access to one TCM (e.g. R5FSS0_CORE0_ATCM) among all access requests from many cores (e.g. R5FSS0_CORE0, R5FSS0_CORE1, A53, M4F).

7)

   

Thanks and Best regards,

Tsurumoto.

  • +1
    TI__Mastermind 27050 points
    Tsurumoto said:
    1) Does AM64x some restriction to access to ATCM (because of ROM code)?

    No restrictions. All 4 R5 cores have their own TCM, including TCMA.

    Tsurumoto said:
    2) Is there other memory that have some access restriction by SW (e.g. ROM code, bootloader, or other SDK code).

    No access restrictions, but see https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/latest/exports/docs/api_guide_am64x/MEMORY_MAP.html for description of MSRAM usage during boot.

    Tsurumoto said:
    3) Is R5FSS0_CORE0_ATCM accessible from R5FSS1_CORE1, right?

    Yes. All TCMs are visible to all cores in the memory map as shown in Table 2-1. MAIN Domain Memory Map . But the latency of TCM access using the main domain memory map is relatively high at over 100ns compared to single cycle to local TCM using the local address . This is benchmarked in 3.1.3 Cortex-R5 Memory Access Latency of https://www.ti.com/lit/pdf/spracv1 .

    Tsurumoto said:

    I think, R5FSS0_CORE0 uses the following direct path to access to R5FSS0_CORE0_ATCM.

         

    Yes, this is single cycle

    Tsurumoto said:

     And, other cores (e.g. R5FSS0_CORE1 the following direct path to access to R5FSS0_CORE0_ATCM.

          

    Yes, this is just over 100ns as shown in the benchmarks app report.

    Tsurumoto said:

    5) How about the access latency to

           - from R5FSS0_CORE0 to R5FSS0_CORE0_ATCM.

           - from R5FSS0_CORE1 to R5FSS0_CORE0_ATCM

           - from other cores (e.g. A53, M4F) to R5FSS0_CORE0_ATCM

    Local address for TCM is single clock cycle (1.25ns), remote core to TCM is >100ns.

    Tsurumoto said:
    6)  How to priories each access to one TCM (e.g. R5FSS0_CORE0_ATCM) among all access requests from many cores (e.g. R5FSS0_CORE0, R5FSS0_CORE1, A53, M4F).

    Local core is able to issue an access every clock cycle, remote cores only about 1/100 clock cycles.