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J721EXSOMXEVM: J721EXSOMG01 board GP mode about HSM security encryption issues

Part Number: J721EXSOMXEVM

1  Can the GP of your TI EVM official board J721EXSOMG01EVM run the secure encryption HSM module? Or does it have to be HS? 

2  I ran vector's autosar secure encryption HSM on the GP version of the EVM official board J721EXSOMG01EVM. When I run the HOST end on the R5F core of the mcu and the HSM end on the Cortex-M3 core, I can load the run separately. However, when I run at the same time, the ccs debugger single-step HOST code will run around and cannot run normally single-step.

  • Hi Chen,

    1  Can the GP of your TI EVM official board J721EXSOMG01EVM run the secure encryption HSM module? Or does it have to be HS? 

    The GP version of the J721E SoCs do have the SA2UL Security Accelerators, but they are not enabled in the TIFS. There is no provision for efusing/programming customer secure keys on a GP device, so true device-security can not be achieved. You will need a HS device to have secure keys. 

    I ran vector's autosar secure encryption HSM on the GP version of the EVM official board J721EXSOMG01EVM. When I run the HOST end on the R5F core of the mcu and the HSM end on the Cortex-M3 core, I can load the run separately. However, when I run at the same time, the ccs debugger single-step HOST code will run around and cannot run normally single-step.

    Please contact Vector for support with thier Vector HSM stack and firmware. TI does not have access to or deliver the Vector HSM firmware by ourselves in the SDK.  

    regards

    Suman

  • Thank you for your support and answers! Now I have bought vector's HSM security encryption package, can I do security encryption development on the GP board of this EVM, or demo development?

  • hi,I also need to confirm that my HSM side is running on the R5F core and my HOST side is running on the Cortex-M core, and it cannot run while running at the same time. I would like to confirm whether it is the hardware of this board or where the setting causes that the two cores cannot run at the same time. If it is a setting or hardware problem, how to operate to ensure that both cores run at the same time.

  • Hi Chen,

    vector's HSM security encryption package, can I do security encryption development on the GP board of this EVM, or demo development?

    Yes, this should be possible in theory. The TI EVMs only come with a GP device, and IIUC, you are customizing the TIFS to add the Vector stack on top of it. You would typically need a HS-Prime device for this.

    hi,I also need to confirm that my HSM side is running on the R5F core and my HOST side is running on the Cortex-M core, and it cannot run while running at the same time. I would like to confirm whether it is the hardware of this board or where the setting causes that the two cores cannot run at the same time. If it is a setting or hardware problem, how to operate to ensure that both cores run at the same time.

    You mean, HOST-side running on R5F, and HSM-side running on Cortex-M core? There are no restrictions. In fact, none of our devices can run/boot without both of them running. The SBL/Bootloader code runs on the MCU R5F, while the TIFS runs on the Cortex-M4 core. 

    regards

    Suman