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AM6442: Processor view memory map

Hirotaka Matsumoto
Guru 27585 points
Part Number: AM6442

Hi all

Would you mind if we ask AM6442 OSPI flashing tools and processor view memory address?

<Question1>
We think MCU+SDK flashing tool's configration file (e.g. default_sbl_ospi.cfg) set offset that SBL = 0x0, .appimage = 0x80000.
Is this processor view memory base address 0x6000_0000?
We referenced TRM 4.8.1 memory layout/mpu Region 11.


<Question2>
If we boot from not OSPI(e.g.eMMC), which region allocate for flash memory?


<Question3>
As the example that gpio_led_blink_am64x_sk_a53ss0-0_nortos project's linker command file allocated 0x800000000 to 0x820000000 for DDR,
how long address the processor view memory map allocated for DDR4? (e.g.0x800000000 to 0xFFFFFFFFF? )


Kind regards,

Hirotaka Matsumoto

  • +1
    TI__Guru 70601 points

    Hello Hirotaka san,

    1/ The OPSI is memory mapped to the main domain memory region named FSS0_DAT_REG1 only in the case of Direct Read/Writes. When performing the Indirect Read/Writes, which are serviced through OSPI Indirect Access Controller (INDAC), the transaction data is serviced through the local SRAM module.

    Now, the MCU+ SDK does not support the Direct Writes. So, while flashing which writes data to flash, the SDK uses indirect writes and so the offsets used are not directly memory mapped to the memory base address of 0x6000_0000.

    2/ In case of eMMC, the data is directly read from or write to the eMMC. The reads & writes are performed directly with the help of eMMC controller.

    3/ 

    Hirotaka Matsumoto said:
    how long address the processor view memory map allocated for DDR4? (e.g.0x800000000 to 0xFFFFFFFFF? )

    Yes, this is correct. The processor view memery map for DDR is of 2GB (0x80000000 - 0xFFFFFFFF).

    Regards,

    Prashant