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controlling C6727B wait state

rsp
Prodigy 70 points

We are using C6727B DSP and using Code Composer Studio with an emulator for debugging. In the GEL file. we are setting the following registers

1. A1CR = 0x3FFFFFFD (16-Bit Data Access)

2. AWCCR = 0x10000080 (Default Value)

We are not presently using EM_WAIT signal.

The EM_CS2 signal pulses for about 2.5 us(High-Low-High) whenever an Asynchronous Memory / IO is accessed. Is the 2.5 us due to the value 80 in MEWC of AWCCR. If I have to reduce this time (faster) what should I do. I tried changing the MEWC to 0x0 but it didn't work. As per the datasheet the EM_CS2 should not take mare than 7-8 cycles of EM_CLK clock. Our EM_CLK is set to 30 MHz. For which we should get a EM_CS2 pulse of about 266 ns.

Pl. Help.

Thank You in Advance,

C6727B user

  • 0
    TI__Guru 64500 points

    I would say your long EM_CS2 pulses probably have more to do with the A1CR register considering you have configured the Extended Wait to be disabled by setting bit 30 (EW) of A1CR to 0.

    The bit fields of the A1CR are specified in Section 3.5 of the TMS320C672x DSP External Memory Interface (EMIF) User's Guide (SPRU711).  The bit fields determine the length, in EM_CLK cycles, of the SETUP, STROBE and HOLD times for Read and Write Accesses.  The timing diagrams depicted the SETUP, STROBE and HOLD times are in Figure 2-13 and Figure 2-14.

    You currently have every field configured to the maximum value.  These should be tuned to your particular memory, or device needs which you have connected to the C6727B EMIF.