TDA4VH-Q1: Pin delay

Xingyu Zhu

Part Number: TDA4VH-Q1

Dear expert,

Do customers need to take the DDR pin delay into consideration when doing layout? And how about other high speed signals, like MIPI eMMC PCIe USB?

In the reference design PROC154E1, customer finds we do not consider the DDR pin delay. So customer needs to follow that? Thanks.

Best Regards,

Xingyu Zhu

over 3 years ago

0 Robert Eschler over 3 years ago

TI__Guru 56945 points

In CDDS there is a S-Param package file that includes package module used when simulating the LPDDR interface. There is also a XLS file that includes the package delays. I've attached here.

TDA4VH_Pkg_DDR_Net_Delay.xlsx

0 Xingyu Zhu over 3 years ago in reply to Robert Eschler

TI__Expert 4335 points

Hi Robert,

Thanks for reply. Based on my understanding, the DDR Delay should be taken into consideration when layout, right? Our customer find our reference design PROC141E4 doesn't contain that. Could you please share your comments? Thanks.

0 Robert Eschler over 3 years ago in reply to Xingyu Zhu

TI__Guru 56945 points

Yes - pin delay (package) should be taken into consideration when layout of a PCB design. Yes - we try to account for these delays when designing our EVMs. Sometimes the EVM and package are designed at same time, and package is not final when EVM is completed.

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TDA4VH-Q1: Pin delay