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[C6747] Switch Central Resource latency

Cristian Bogus
Prodigy 140 points

Hi Everyone,

I'm concerned about the potential lantencies introduced by the SCR in an C6747 alone or (C6747 + ARM) architecture.

Is any figure (max value/cycles available)?

Is there any possibility of deadlock if (for instance) two interrupts runing on the same component DSP or ARM access a peripheral? 

Example 1:

For instance,  function A access a peripheral when function B interrupts function A and try to access the same peripheral but cannot do it since the SCR is waiting for function A to free it... Can this situation occur ? Any specific methods to prevent it?

Example 2:

Function A access peripheral A very often, Function B trys to access peripheral B but the accesses have a jitter since the SCR is busy with accesses to peripheral A? What would be the maximum jitter value (expressed in cycles)?

 

Regards,

Cristian

  • 0
    TI__Guru*** 125430 points

    The SCR was introduced to eliminate data bottlenecks and to dramatically increase the amount of throughput in the chip.  This adds some additional logic and hence additional delay in the path.  There are no specs on that delay.  Really such specs would not be of much value because there are so many other things to consider such as the latency of the peripheral being accessed and what other transfers are also happening.

    There's no possibility for deadlock on SCR because the DMA masters are not actually given "ownership" of the bus.  Instead the SCR itself arbitrates on a cycle-by-cycle basis (though it allows burst transfers for better efficiency too, so in that case it would arbitrate on a burst by burst basis).

    Yes, there would be some "jitter" as you put it due to one master holding off another.  It's up to you to program the appropriate priorities based on how the masters will be accessing the peripheral.

    Brad