Hello,
I have some doubts about the clock source selection to configure the McBsp Sample rate generator on a C6457 device.
In the datasheet of the device (sprs582b) the PLL1 section shows with the figure 7-12 that SYSCLK5 and SYSCLK6 are routed to McBsp and at page 131 is reported that
"SYSCLK5: 1/6-rate clock (CHIP_CLK6) for other peripherals (PLL controller, PSC, L3 ROM, McBSPs, Timer64s, EMAC, HPI, UTOPIA, I2C, and GPIO).
SYSCLK6: 1/y-rate clock (CHIP_CLKS) for an optional McBSP CLKS module input to drive the clock
generator. The default for this clock is 1/10. This is programmable from /6 to /32, where this clock does not
violate the maximum clock rate of 100 MHz. This clock is also output to the SYSCLKOUT pin."
After reading this I thought that I could use SYSCLK6 (which is programmable while SYSCLK5 has a locked divider) as internal clock for the McBsp sample rate generator. But reading the C6457 McBsp User guide (sprugk8A revised on March 2010) I found the Figure 3 at pag 15 which shows that the internal clock source for the sample rate generator is CPU/4 and in the same document it is also written at pag 18 (par. 4.3 Data clock generation) that:
" The input clock to the sample rate generator, which can be either the internal clock source or a dedicated external clock source (CLKS). The C6457 device uses the CPU/6 clock as the internal clock source to the sample rate generator."
So at this point I am a little confused and I have the following questions
1) Which is the internal clock source for the sample rate generator between SYSCLK5, SYSCLK6 and CPU/4?
2)If possible, how do I select the internal clock source between SYSCLK6 and SYSCLK5?
Thank you for any help!
Alessandro
