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Hello, TI expert
I would like to conduct a test using an external server as a software clock source. In this test, I want to use eth0 of the EVM as the transparent clock and eth1 of the EVM as the clock that needs to be synchronized. The synchronization order should be server -> eth0 -> eth1. How can I achieve this?
Hi,
eth0 cannot be a transparent clock as a transparent clock has two interfaces. So I am not very clear on your setup.
But, you can use phc2sys to synchronize the hardware clock corresponding to eth0 and eth1. Foe more details on how to do hat, please see manual page of phc2sys. Also which CPSW would theteh0 and eeth1 correspond to in your case? By default they are in different CPSW instances. But if they are in same CPSW instance, they would share the CPTS clock used for PTP and and will be synchronized by default.
Regards,
Tanmay
thanks,This solved some of my problems
Can cpsw2G and CPSW9G be connected? How to configure a virtual local area network?
Hi,
Can cpsw2G and CPSW9G be connected?
If you mean externally, then yes, they can be connected.
How to configure a virtual local area network?
Please see this https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/08_06_01_02/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW2g.html#cpsw2g for the same.
Regards,
Tanmay