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Original question:

SK-AM64B: DDRSS memory capacity range question

SK-AM64B: SK-AM64B: DDRSS memory capacity range question

Huynh Nguyen
Prodigy 240 points
Part Number: SK-AM64B

So if designing LPDDR4 the second rank (DDR0_CS1_N) cannot be used ? If so was it usable in the regular DDR4 component ?

  • 0
    TI__Expert 3905 points

    Greetings Huynh,

    I'm not sure exactly what you're asking, can you clarify if you are asking about the different addressing options between DDR4 and LPDDR4?

    Sincerely,

    Lucas

  • +1 in reply to Lucas Bowe
    TI__Guru* 77730 points

    Huynh, 

    correct, we only support single rank design with AM64x for both LPDDR4 and DDR4

    Regards,

    James

  • +1 in reply to JJD
    Prodigy 240 points

    Thank you for clarification. So the next question is what is the use or purpose of DDR0_CS1_N? Is it something for future expansion or is it possible we use 2 devices (for 2 separate chip selects) of single rank LPDDR4/DDR4 ? 

    Also I need the explanation of the AM64xx TRM section 8.1.1 (DRSS Overview) where it said Memory Bus Features of up to  2 ranks and  SDRAM address range up to 8GB. But the section 8.1.1.1 (DDRSS Not Supported Features) indicated : only 1 rank design is supported and up to 2GB dram space. So what is the purpose of the feature set in 8.1.1.

    Thanks,

    Huynh

  • 0 in reply to Huynh Nguyen
    TI__Guru* 77730 points

    Huynh, the DDR IP supports dual rank, but we deprecated that feature in AM64x, so this pin is not used.  It may be enabled in the future, but most likely it will not as signal rank 2GB devices are easily available.

    The feature set in 8.1.1 describes the DDR IP feature set, some of which can be deprecated as described in the Not Supported Features section

    Regards,

    James