I am using AM5706 as PCIe 1.0 two Root-complex of x1 lane
We are following two approach for the ref clock of PCIe.
One is providing external input to PCIe Clk. What is the input/Output driver of LJCB_CLKP. Is it HCSL or LVDS?
The latter one is, output from LJCB_CLKP is buffered to other endpoints.
So, if it is an HCSL output, I have to provide external 50 Ohm termination to gnd right?
