AM5748:

Hello Josue,

Thank you for the reply and sharing those documents.

The above option will be meeting my data acquisition requirement, right?

Arun,

After an internal discussion I believe your data acquisition should be achievable with help of this part ADS127L11 using standard SPI or the PRU pins.

I am double-checking that the PRU-ICSS firmware for AM57x will support the GPIO functionality aforementioned in the reference design. I will post the conclusion here once I get confirmation.

Hi Josue..

Any update on this. 

We need atleast 8 ADC channels. So we have selected AD4134 for this purpose. 

The selected ADC got an SPI interface for its configuration and a data interface has got 4 digital channels which will be outputting simultaneously the 4 channel outputs DOUT0, DOUT1, DOUT2, and DOUT3.

I am planning to use one of the SPI channel for the register access. But I am not sure about the Data interface for ADC data read.

Pls provide solutions to the below questions?

1. Is it possible to use DSP for the data read? If yes, Can I connect these pins to any of the GPIO pins of the DSP?

2. Can I use the McASP interface?

3. Interface Using the PRU core taking DCLK and Dout pins as GPO and GPI pins respectively

Pls suggest a best solution to interface the ADC to the SoM

Hello Arun,

I will need some time to answer your question. I will reply back by next week.

-Josue

Hello Josue,

Thank you for the reply

Hello Josue,

Thank you for the reply.

For the McASP interface, we are not planning to use as a GPIO, but to use the AXR,AFSR and ACLKR pins and to use the ADC in master/slave mode.

Fig1: ADC in master mode

Fig 1: ADC in slave mode

Here we have selected AD4134 for ADC due to our resolution and scan rate requirements.

AD4134 has 4 dedicated Dout pins to simultaneously output the data and DCLK and ODR for sync as discussed earlier; and there is an option to configure AD4134 in such a way that it can output the 4 channel data through SDO pin of SPI. I Do the native SPI interface ensure deterministic data transfers?

We are planning use the Critical Link's MitySOM AM57F SoM for our design which has an FPGA core also along with the AM57x core.

So our current options are

1. Use FPGA to receive the data from the ADC and sends it to the AM57 processor over the PCIe bus for further processing

2. Use the PRU core of AM57x to receive the data and arm core can access the data over shared memory.

Please share you opinion on these 2 stratergies.

Also, in our design, we have to use 4 AD4134 modules to meet our requirements.

Regards,

Arun

We support somewhat close use cases in the AM64x family, with support for https://www.ti.com/product/ADS8598H (18-bit, 8-ch, 500kSPS) and https://www.ti.com/product/ADS127L11 (24-bit, single channel, 1MSPS). There are examples of connecting to these using the ICSS-PRU in the SDK https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/latest/exports/docs/api_guide_am64x/EXAMPLES_PRU_ADC.html and https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/latest/exports/docs/api_guide_am64x/DRIVERS_PRU_ADC.html#autotoc_md1841 . You could take a look at that, the ADS8598H example with 8 and 16 bit parallel might be close to the 4-bit parallel interface it looks like the AD4134 uses. Maybe 2x ADS8598H would fit? Also running 16xADS127L11 should be possible and would get you to 16-channels at 24-bit.

We don't currently have these examples ported to AM5748.

  Pekka