AM62A7-Q1: About the Power PIN decoupling capacitors

Hello Haiming Qu,

Thank you for the query.

This is a recommendation for customer to follow. It is up to the customer to follow since they understand their systems better.

Please refer to the DDR design guide that recommends performing simulation.

https://www.ti.com/lit/an/sprad66/sprad66.pdf

TI's EVM should still be used as a starting point, and simulations must be performed. The customer design may need to constrain the interface frequency/data rate based on the PCB implementation.

The EVM leverages 3-terminal (3-T) very low ESL capacitors to achieve recommended power rail impedance performance (ZvsF response) especially on heavily loaded voltage domains (i.e. VDD_CORE, VDDR_CORE, VDD_LPDDR4).

Power integrity simulations using 3-D extraction tools to accurately model power via impedance at frequencies above ~3.0 MHz has shown that ~6-8pcs of standard 2-terminal (2-T) caps are needed for each 3-T cap in order to achieve similar power rail impedance performance. So using 3-T caps vs 2-T caps actually reduces the total qty & PCB area needed to achieve same decoupling performance.

Please note that i do not have any simulation results that can be shared.

Haiming Qu said:

If we use normal X7R cap to replace them, what issue will happen?

This is customer choice. Customers need to ensure the equivalent capacitance shown in the EVM is available for the supply rails under all operating conditions.

Loop inductance is more important than capacitance when good performance from a decoupling capacitor is required.  You can add lots of capacitance, but the capacitance will not be effective if loop inductance is high.  The loop inductance is higher in two terminal capacitors.  That is why we are using three terminal capacitors. 

FYI, Using 3-T caps has little to no impact on overall BOM cost since cost of 6-8pcs of 2-T caps is similar to 1x 3-T cap.

You might want to read through the information available on 3T caps vs 2T caps.

Regards,

Sreenivasa

Hello Haiming Qu,

FYI, the device characterization internally has been performed with the 3 terminal caps populated as shown in the EVM.

Regards,

Sreenivasa

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Hello Haiming Qu,

Thank you for the note.

I will close the thread.

Regards,

Sreenivasa