Were I can find drivers for THS8200
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Eli,
Depending on how the THS8200 is connected specific drivers may not be needed as such.
If the THS8200 is connected and configured as a generic RGB DAC and the syncs are passed directly from the DSP through level shifters then only a simple initialization is required, with all other configuration done through fbdev timing settings as per the generic 24 bit digital RGB DVO output.
Bottom line, we do not have a specific driver since it depends very much on how the THS8200 is connected.
BR,
Steve
Hi,
We have used THS8200 on DM6467T over 16bit embedded sync mode. You can get the THS8200 driver for this mode from arago tree.
Thanks,
Brijesh Jadav
Hi,
Please find it at below location.
http://arago-project.org/git/projects/?p=linux-davinci.git;a=blob;f=drivers/media/video/ths8200.c;h=1bfe8ae46aca8c58b63b6381dc3c01356a1be70c;hb=DAVINCIPSP_03.21.00.02
Thx,
Brijesh Jadav
Hi,
See below customer feedbac/questions:
My application is using the THS8200 on the output of a Video Scaler. The output format can vary from 480p to 1080p and have also a lot of VESA output standards. The output of the THS8200 is for a "VGA" output of the Scaler on a 15p DB connector with RGBHV output. The Scaler output is YUV 30 bit wide + H, V, DE controls. So I need the color space converter and I assume that the output mode is VESA mode. Do I need to configure the DTG timing registers for every VESA Standard? The HV signals from the Scaler already have the correct timing. If I need to configure the DTG does TI have a set of settings for the VESA standards?
Thanks in advance for your feedback
Eli
Hi eli,
We dont have VESA standard supported on this driver. You will need to program DTG to generate VESA mode output.
I did not get how scalar output is connected to THS8200 over 30 bit interface. Scalar typically outputs YUV422 data on 16 bit interface.
thanks,
Brijesh Jadav
Eli,
Try the settings below which set up the THS8200 as a generic DAC. The CSC and CSM are enabled to convert from reduced range YCbCr to RGB. In this mode of operation you should be able to bypass the THS8200 with the syncs and directly connect the scaler syncs to the monitor.
This appears to produce correct RGB levels as long as DE is not required to force a blank/black level. This should be OK as long as the scaler is outputting correct black levels for YCbCr during blanking.
//THS8200 Generic DAC setup
WR_REG,THS8200,0x01,0x03,0xC1 // chip_ctl
WR_REG,THS8200,0x01,0x1C,0x70 // dman_cntl 24/30-bit input
WR_REG,THS8200,0x01,0x38,0x07 // dtg_mode VESA mode DTG off
WR_REG,THS8200,0x01,0x82,0x1B // pol_cntl DE disabled
//CSC Setup
WR_REG,THS8200,0x01,0x04,0x81 // csc_ric1
WR_REG,THS8200,0x01,0x05,0xD5 // csc_rfc1
WR_REG,THS8200,0x01,0x06,0x00 // csc_ric2
WR_REG,THS8200,0x01,0x07,0x00 // csc_rfc2
WR_REG,THS8200,0x01,0x08,0x06 // csc_ric3
WR_REG,THS8200,0x01,0x09,0x29 // csc_rfc3
WR_REG,THS8200,0x01,0x0A,0x04 // csc_gic1
WR_REG,THS8200,0x01,0x0B,0x00 // csc_gfc1
WR_REG,THS8200,0x01,0x0C,0x04 // csc_gic2
WR_REG,THS8200,0x01,0x0D,0x00 // csc_gfc2
WR_REG,THS8200,0x01,0x0E,0x04 // csc_gic3
WR_REG,THS8200,0x01,0x0F,0x00 // csc_gfc3
WR_REG,THS8200,0x01,0x10,0x80 // csc_bic1
WR_REG,THS8200,0x01,0x11,0xBB // csc_bfc1
WR_REG,THS8200,0x01,0x12,0x07 // csc_bic2
WR_REG,THS8200,0x01,0x13,0x42 // csc_bfc2
WR_REG,THS8200,0x01,0x14,0x00 // csc_bic3
WR_REG,THS8200,0x01,0x15,0x00 // csc_bfc3
WR_REG,THS8200,0x01,0x16,0x14 // csc_offset1
WR_REG,THS8200,0x01,0x17,0xAE // csc_offset12
WR_REG,THS8200,0x01,0x18,0x8B // csc_offset23
WR_REG,THS8200,0x01,0x19,0x15 // csc_offset3
//CSM setup to map reduced range YCbCr to FS RGB
WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low
WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low
WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low
WR_REG,THS8200,0x01,0x44,0x53 // csm_clip_gy_high
WR_REG,THS8200,0x01,0x45,0x3F // csm_clip_bcb_high
WR_REG,THS8200,0x01,0x46,0x3F // csm_clip_rcr_high
WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy
WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb
WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr
WR_REG,THS8200,0x01,0x4A,0xFC // csm_mult_gy_msb
WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
WR_REG,THS8200,0x01,0x4C,0xAC // csm_mult_gy_lsb
WR_REG,THS8200,0x01,0x4D,0xAC // csm_mult_bcb_lsb
WR_REG,THS8200,0x01,0x4E,0xAC // csm_mult_rcr_lsb
WR_REG,THS8200,0x01,0x4F,0xFF // csm_mode
Hi Tary,
This setup Does not output Hsync and Vsync from the chip. Customer added a bypass wire to have the syncs to the output buffer.
Is it possible to have the output pins working with only passing the input to output ? IS it possible to have the syncs output with the added delay of the internal process of the DAC + CSC + CSM ?
Eli,
The THS8200 does not have a simple sync bypass mode where the inputs syncs pass through the THS, with delay matching. The THS8200 sync polarity and widths must be uniquely programmed for each graphics format, however the process delay will be constant for all formats. Attached is a setup file which includes numerous 30-bit graphics setups. Thjis files has common settings and unique settings requrried for the various formats.
Regards,
Larry