Hi,
We are using AM625x in our design. We are using RMII to interface AM625x with ethernet PHY DP83620SQE.
We are currently testing our board and are seeing packet drop in TX. However RX is ok. To debug this issue we probed the RMII signals on the TX and RX lines while doing a ping, and following is our observation.
RMII TX: We are observing the voltage levels on TX signals which are driven by AM625x as 1.5V approx, when measured near the processor side. The hardware configuration for RMII is to work at 3.3V. But why these signals(TXD0,TXD1) are at a lesser voltage? Any fw configurations we need to set for the voltage levels? or is RGMII getting enabled? Please share your thoughts on this.
However, the TX Enable signal is at 3V.
TX clock and TXD:
TX Enable and TXD:
RMII RX:For receive we are able to see the signals at proper voltage levels, at 3.3V.
Also we want to know, how processor knows if we are using external or internal clock source for RMII? Is there any configurations for it? We are currently using External clock source for our design. any setting needs to be done in Fw for this?
Kindly let us know why TX signals are driven at a voltage which is not 3.3V.
