Part Number: AM625
Hi experts
I have a AM62 McASP HW design issue.
In customer’s application, they need many output audio channels(they are focusing on PAVA-public address/evacuate alarm), they use at least four DAC that all need MCLK input. AM6254 has 2 AUDIO_EXT_REFCLK, one they used it as input, another AUDIO_EXT_REFCLK could be output, but one clock connects to 4 DACs is not proper design. So I bring a clock buffer to their design, the clock buffer should feature very low skew to keep all audio channel synced.
Do you think this scheme is doable?
Do you have any better solution?
