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RapidIO (SRIO) - writting to LSU command regs when BSY bit set

Eddie3909
Guru 10385 points


Hi

Can the LSU trigger an interrupt when the LSU command registers are written to when the BSY bit is asserted?

sprue13j.pdf: Upon completion of the write to the command register (next clock cycle T5), the BSY
signal is asserted, at which point the preceding completion code is invalid and accesses to the LSU
registers are not allowed.

We're evaluating the use of an external GPIO pin to sync the EDMA used for streaming instead of the BSY signal and would like to know if there is a way to detect this error.

Cheers

 

  • 0
    TI__Mastermind 23525 points

    Eddie,

    Any writes to the LSU registers while the BSY bit is set, will be ignored.  So you could have race condition issues if you try something like this.  For example, say the BSY bit is high, and you start to write the first couple LSU registers, which is ignored.  Then the preceding LSU transaction completes, the interrupt is fired and the BSY bit goes low, then the remaining LSU writes, including the command register are written.  You will have some mixed state of LSU registers for that transaction, and it will cause issues.  You definitely need to wait until the bsy bit is low, or the interrupt occurs before trying to write the registers.

     

    Regards,

    Travis