I am using the I2C module in master mode with RM=1 (repeat mode).
The communication should look like this:
- START (r/w=0)
- send some bytes to the slave
- RESTART (r/w=1)
- receive one byte from the slave
- STOP
Everything works fine (the bus analyzer shows that all data is transmitted and received as expected and every byte gets ACKed), but the I2C module doesn't generate the STOP condition at the end (and it doesn't release the SCL line).
To generate the STOP condition I do the following:
while(!I2C_FGETH(i2c0,I2CSTR,ICRRDY)); // wait until data is ready to read
data = I2C_readByte(i2c0); // read data (see step 4 above)
while(!I2C_FGETH(i2c0,I2CSTR,ARDY)); // wait until ready to access registers
I2C_FSETSH(i2c0,I2CMDR,STP,STOP); // try to generate the STOP condition (see step 5 above)
After that, the I2CMDR register has the value 0x00004CA0, which means that the STP bit has not been cleared. The status register (I2CSTR) has the value 0x00001C1C, which shows that the bus is still in use (BB=1) and it also shows an overrun (RSFULL=1) and an underflow (XSMT=1)...
Robert