Hello Champs,
Customer used FPGA to provide 8.192MHz clock to C6678 TSIP and a SYNC signal every 1024 clocks as below.
1. Modify below parameters in TSIP_exampleProject
cfg->tx.tsPerFrame = 128;
cfg->tx.dataRate = CSL_TSIP_DATARATE_8M;
cfg->tx.clkMode = CSL_TSIP_CLKM_SGL;
2. After loading .out file, the first non-zero data received in TsipToAppBuffer is 31 instead of 1. Why? How to resolve it?
Thanks
Regards
Shine