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TDA4VH-Q1: TDA4VH performance issue

li quan
Intellectual 955 points

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Hi expers,  

We encountered a performance issue on on the tda4vh platform (SDK8.6).  We found that the DDR bandwidth can only reach 20GB/S (utilization rate about 31%), and the CPU load is 75% when our algorithm running. 

After our investigation，the performance bottleneck lies in the slow DDR access speed.

But we can only monitor the total DDR bandwidth, is there any way to monitor the ddr bandwidth of each master (dru a72 or r5 and so on) accessing.

Thanks

quanli

  • 0
    TI__Guru**** 502325 points

    Hi quanli,

    Unfortunately, no, in the current SDK, it is not supported. But for most of the masters, BW can easily be calculated, like for CSIRX, it is just w x h x Bpp x fps. So you can calculate BW for most of these fixed modules. 

    Btw, on which core are you seeing utilization to be 75%? 

    Regards,

    Brijesh