TDA4AL-Q1: Failed to boot TDA4AL from eMMC UDA partition using SBL

li liu

Part Number: TDA4AL-Q1

Hello TI Expert，

I encountered the same problem as this,even the error log is the same

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1244060/tda4vm-failed-to-boot-tda4vm-from-emmc-uda-partition-using-sbl-in-sdk-8-4/4709333?tisearch=e2e-sitesearch&keymatch=SBL%2525252520EMMC#4709333

NOTICE:  BL31: Built : 10:56:05, May 29 2023
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: 
I/TC: OP-TEE version: 97dc684 (gcc version 9.4.0 (Ubuntu 9.4.0-1ubuntu1~20.04.1)) #1 Mon May 29 02:56:44 UTC 2023 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--v08.06.03 (Chill Capybar')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[    0.000000] Linux version 5.10.162-g76b3e88d56 (wangzi@wangzi) (aarch64-none-linux-gnu-gcc (GNU Toolchain for the A-profile
 Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025, GNU ld (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.
10)) 2.33.1.20191209) #1 SMP PREEMPT Tue Jul 11 15:28:52 CST 2023
[    0.000000] Machine model: Texas Instruments J721S2 EVM
[    0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '')
[    0.000000] printk: bootconsole [ns16550a0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a0000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a0100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a1000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a1100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a2000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a2100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a4000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a4100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a6000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a6100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a7000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a7100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8000000, size 32 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-rtos-ipc-memory-region@a8000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000aa000000, size 96 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-dma-memory@aa000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b0000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71-dma-memory@b0000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b0100000, size 95 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71_0-memory@b0100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b6000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71_1-dma-memory@b6000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b6100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71_1-memory@b6100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: initialized node vision_apps_shared-memories, compatible id dma-heap-carveout
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000d8000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-core-heap-memory-lo@d8000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000880000000, size 704 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-core-heap-memory-hi@880000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x00000008ac000000, size 896 MiB
[    0.000000] OF: reserved mem: initialized node linux-cma-buffers@8ac000000, compatible id shared-dma-pool
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000080000000-0x00000000ffffffff]
[    0.000000]   DMA32    empty
[    0.000000]   Normal   [mem 0x0000000100000000-0x00000008ffffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080000000-0x000000009e7fffff]
[    0.000000]   node   0: [mem 0x000000009e800000-0x00000000b7ffffff]
[    0.000000]   node   0: [mem 0x00000000b8000000-0x00000000d7ffffff]
[    0.000000]   node   0: [mem 0x00000000d8000000-0x00000000dbffffff]
[    0.000000]   node   0: [mem 0x00000000dc000000-0x00000000ffffffff]
[    0.000000]   node   0: [mem 0x0000000880000000-0x00000008abffffff]
[    0.000000]   node   0: [mem 0x00000008ac000000-0x00000008ffffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff]
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.2
[    0.000000] percpu: Embedded 22 pages/cpu s50392 r8192 d31528 u90112
[    0.000000] Detected PIPT I-cache on CPU0
[    0.000000] CPU features: detected: GIC system register CPU interface
[    0.000000] CPU features: detected: EL2 vector hardening
[    0.000000] CPU features: kernel page table isolation forced ON by KASLR
[    0.000000] CPU features: detected: Kernel page table isolation (KPTI)
[    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[    0.000000] CPU features: detected: Spectre-BHB
[    0.000000] CPU features: detected: ARM erratum 1742098
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1032192
[    0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2800000 root=/dev/mmcblk0p2 rw rootfstyp
e=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
[    0.000000] Memory: 1383904K/4194304K available (11712K kernel code, 1192K rwdata, 4468K rodata, 1984K init, 456K bss, 1892
896K reserved, 917504K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2.
[    0.000000]  Trampoline variant of Tasks RCU enabled.
[    0.000000]  Tracing variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: 960 SPIs implemented
[    0.000000] GICv3: 0 Extended SPIs implemented
[    0.000000] GICv3: Distributor has no Range Selector support
[    0.000000] GICv3: 16 PPIs implemented
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
[    0.000000] ITS [mem 0x01820000-0x0182ffff]
[    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[    0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19
[    0.000000] ITS@0x0000000001820000: allocated 524288 Devices @8e4800000 (flat, esz 8, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GICv3: using LPI property table @0x00000008e4030000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] GICv3: CPU0: using allocated LPI pending table @0x00000008e4040000
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[    0.000002] sched_clock: 56 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[    0.008387] Console: colour dummy device 80x25
[    0.012958] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
[    0.023629] pid_max: default: 32768 minimum: 301
[    0.028388] LSM: Security Framework initializing
[    0.033151] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.040735] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.049710] rcu: Hierarchical SRCU implementation.
[    0.054806] Platform MSI: msi-controller@1820000 domain created
[    0.061049] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
[    0.070358] EFI services will not be available.
[    0.075105] smp: Bringing up secondary CPUs ...
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
[    0.094043] Detected PIPT I-cache on CPU1
[    0.094071] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
[    0.094083] GICv3: CPU1: using allocated LPI pending table @0x00000008e4050000
[    0.094125] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
[    0.094184] smp: Brought up 1 node, 2 CPUs
[    0.123535] SMP: Total of 2 processors activated.
[    0.128341] CPU features: detected: 32-bit EL0 Support
[    0.133596] CPU features: detected: CRC32 instructions
[    0.148787] CPU: All CPU(s) started at EL2
[    0.152997] alternatives: patching kernel code
[    0.158145] devtmpfs: initialized
[    0.166431] KASLR disabled due to lack of seed
[    0.171103] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.181071] futex hash table entries: 512 (order: 3, 32768 bytes, linear)
[    0.203154] pinctrl core: initialized pinctrl subsystem
[    0.208885] DMI not present or invalid.
[    0.213184] NET: Registered protocol family 16
[    0.218670] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
[    0.225988] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[    0.233999] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.242146] ramoops: using module parameters
[    0.246575] ramoops ramoops: no room for dmesg mem region (0xffffffffffffe000@0xdd000000) in (0x40000@0xdd000000)
[    0.257073] ramoops: probe of ramoops failed with error -12
[    0.262981] thermal_sys: Registered thermal governor 'step_wise'
[    0.262984] thermal_sys: Registered thermal governor 'power_allocator'
[    0.269626] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.283281] ASID allocator initialised with 32768 entries
[    0.289522] printk: console [ramoops-1] enabled
[    0.294160] pstore: Registered ramoops as persistent store backend
[    0.300474] ramoops: using 0x40000@0xdd000000, ecc: 0
[    0.322128] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
[    0.328989] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages
[    0.335845] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.342695] HugeTLB registered 64.0 KiB page size, pre-allocated 0 pages
[    0.350296] cryptd: max_cpu_qlen set to 1000
[    0.356560] k3-chipinfo 43000014.chipid: Family:J721S2 rev:SR1.0 JTAGID[0x0bb7502f] Detected
[    0.365688] vsys_3v3: supplied by evm_12v0
[    0.370071] vsys_5v0: supplied by evm_12v0
[    0.374958] iommu: Default domain type: Translated 
[    0.380128] SCSI subsystem initialized
[    0.384057] usbcore: registered new interface driver usbfs
[    0.389680] usbcore: registered new interface driver hub
[    0.395121] usbcore: registered new device driver usb
[    0.400555] mc: Linux media interface: v0.10
[    0.404932] videodev: Linux video capture interface: v2.00
[    0.410567] pps_core: LinuxPPS API ver. 1 registered
[    0.415639] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.424982] PTP clock support registered
[    0.429005] EDAC MC: Ver: 3.0.0
[    0.432898] FPGA manager framework
[    0.436428] Advanced Linux Sound Architecture Driver Initialized.
[    0.443111] clocksource: Switched to clocksource arch_sys_counter
[    0.449442] VFS: Disk quotas dquot_6.6.0
[    0.453501] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    0.463397] Carveout Heap: Exported 512 MiB at 0x00000000b8000000
[    0.469704] NET: Registered protocol family 2
[    0.474500] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
[    0.483186] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
[    0.491963] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
[    0.500170] TCP bind hash table entries: 32768 (order: 7, 524288 bytes, linear)
[    0.507965] TCP: Hash tables configured (established 32768 bind 32768)
[    0.514820] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
[    0.521722] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
[    0.529154] NET: Registered protocol family 1
[    0.533941] RPC: Registered named UNIX socket transport module.
[    0.540004] RPC: Registered udp transport module.
[    0.544824] RPC: Registered tcp transport module.
[    0.549629] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.556214] NET: Registered protocol family 44
[    0.560762] PCI: CLS 0 bytes, default 64
[    0.565212] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available
[    0.576019] Initialise system trusted keyrings
[    0.580685] workingset: timestamp_bits=46 max_order=20 bucket_order=0
[    0.589002] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.595376] NFS: Registering the id_resolver key type
[    0.600574] Key type id_resolver registered
[    0.604848] Key type id_legacy registered
[    0.608973] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    0.615824] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    0.623485] 9p: Installing v9fs 9p2000 file system support
[    0.648592] Key type asymmetric registered
[    0.652781] Asymmetric key parser 'x509' registered
[    0.657784] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
[    0.665344] io scheduler mq-deadline registered
[    0.669971] io scheduler kyber registered
[    0.675637] pinctrl-single 4301c000.pinctrl: 101 pins, size 404
[    0.681865] pinctrl-single 11c000.pinctrl: 72 pins, size 288
[    0.692706] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
[    0.705952] brd: module loaded
[    0.713205] loop: module loaded
[    0.717222] megasas: 07.714.04.00-rc1
[    0.723045] tun: Universal TUN/TAP device driver, 1.6
[    0.728571] igbvf: Intel(R) Gigabit Virtual Function Network Driver
[    0.734981] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[    0.741062] sky2: driver version 1.30
[    0.745505] VFIO - User Level meta-driver version: 0.3
[    0.751466] i2c /dev entries driver
[    0.755941] sdhci: Secure Digital Host Controller Interface driver
[    0.762264] sdhci: Copyright(c) Pierre Ossman
[    0.766923] sdhci-pltfm: SDHCI platform and OF driver helper
[    0.773315] ledtrig-cpu: registered to indicate activity on CPUs
[    0.779675] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    0.786598] ashmem: initialized
[    0.790732] optee: probing for conduit method.
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled
[    0.795304] optee: revision 3.20 (97dc6845)
[    0.811696] optee: dynamic shared memory is enabled
[    0.821184] optee: initialized driver
[    0.826440] NET: Registered protocol family 17
[    0.831084] 9pnet: Installing 9P2000 support
[    0.835491] Key type dns_resolver registered
[    0.839962] Loading compiled-in X.509 certificates
[    0.846091] pstore: Invalid compression size for deflate: 0
[    0.858527] ti-sci 44083000.system-controller: ABI: 3.1 (firmware rev 0x0008 '8.6.3--v08.06.03 (Chill Capybar')
[    0.894824] omap_i2c 42120000.i2c: bus 0 rev0.12 at 100 kHz
[    0.901069] omap_i2c 40b00000.i2c: bus 1 rev0.12 at 100 kHz
[    0.907165] omap_i2c 40b10000.i2c: bus 2 rev0.12 at 100 kHz
[    0.913519] pca953x 3-0021: supply vcc not found, using dummy regulator
[    0.920351] pca953x 3-0021: using no AI
[    0.947154] pca953x 3-0021: failed writing register
[    0.952202] pca953x: probe of 3-0021 failed with error -121
[    0.958141] pca953x 3-0020: supply vcc not found, using dummy regulator
[    0.964964] pca953x 3-0020: using no AI
[    0.968937] pca953x 3-0020: failed writing register
[    0.973971] pca953x: probe of 3-0020 failed with error -121
[    0.979865] pca953x 3-0022: supply vcc not found, using dummy regulator
[    0.986670] pca953x 3-0022: using AI
[    0.990375] pca953x 3-0022: failed writing register
[    0.995403] pca953x: probe of 3-0022 failed with error -121
[    1.001141] omap_i2c 2000000.i2c: bus 3 rev0.12 at 400 kHz
[    1.007596] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 125 domain created
[    1.016186] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 148 domain created
[    1.025551] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 227 domain created
[    1.034203] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 265 created
[    1.043950] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[    1.051628] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[    1.059906] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[    1.068194] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    1.077277] ti-udma 311a0000.dma-controller: Number of rings: 48
[    1.084046] ti-udma 311a0000.dma-controller: Channels: 24 (bchan: 0, tchan: 8, rchan: 16)
[    1.093352] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:272
[    1.103245] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[    1.110012] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[    1.118980] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[878,128] sci-dev-id:259
[    1.129150] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    1.135912] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[    1.143608] omap8250 40a00000.serial: failed to get alias
[    1.149768] printk: console [ttyS2] disabled
[    1.154175] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 25, base_baud = 3000000) is a 8250
[    1.162926] printk: console [ttyS2] enabled
[    1.162926] printk: console [ttyS2] enabled
[    1.171364] printk: bootconsole [ns16550a0] disabled
[    1.171364] printk: bootconsole [ns16550a0] disabled
[    1.185159] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
[    1.231121] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.239614] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver unknown
[    1.247671] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports
: 2 quirks:00000000
[    1.260556] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    1.267766] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    1.274118] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:0
[    1.284453] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010c, freq:200000000, add_val:4 pps:0
[    1.394184] mmc0: CQHCI version 5.10
[    1.401240] vdd_mmc1: supplied by vsys_3v3
[    1.406418] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fca100
[    1.413303] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fca100
[    1.420125] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fca100
[    1.426936] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fca100
[    1.433715] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[    1.441210] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[    1.443539] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit
[    1.449294] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[    1.464841] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    1.473965] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8)
[    1.484067] ti-udma 31150000.dma-controller: Channels: 60 (tchan: 30, rchan: 30, gp-rflow: 16)
[    1.494936] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
[    1.525330] mmc0: Command Queue Engine enabled
[    1.529785] mmc0: new DDR MMC card at address 0001
[    1.534934] mmcblk0: mmc0:0001 8GUF4R 7.28 GiB 
[    1.539127] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.539557] mmcblk0boot0: mmc0:0001 8GUF4R partition 1 31.9 MiB
[    1.548010] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver unknown
[    1.553133] mmcblk0boot1: mmc0:0001 8GUF4R partition 2 31.9 MiB
[    1.561105] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports
: 2 quirks:00000000
[    1.567026] mmcblk0rpmb: mmc0:0001 8GUF4R partition 3 4.00 MiB, chardev (236:0)
[    1.579843] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    1.587733]  mmcblk0: p1 p2
[    1.594205] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    1.603194] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:0
[    1.613144] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[    1.621885] mmc1: CQHCI version 5.10
[    1.621914] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[    1.632973] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[    1.641064] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[    1.649153] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    1.658570] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[    1.666085] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[    1.674171] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[    1.678607] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit
[    1.682253] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    1.699070] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[    1.706575] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[    1.714720] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[    1.722861] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    1.731433] debugfs: Directory 'pd:39' with parent 'pm_genpd' already present!
[    1.738811] debugfs: Directory 'pd:38' with parent 'pm_genpd' already present!
[    1.746683] debugfs: Directory 'pd:276' with parent 'pm_genpd' already present!
[    1.754682] debugfs: Directory 'pd:154' with parent 'pm_genpd' already present!
[    1.767666] ALSA device list:
[    1.770632]   No soundcards found.
[    1.777013] mmc0: running CQE recovery
[    1.781018] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000040
[    1.789795] Mem abort info:
[    1.792585]   ESR = 0x96000004
[    1.795634]   EC = 0x25: DABT (current EL), IL = 32 bits
[    1.800937]   SET = 0, FnV = 0
[    1.803988]   EA = 0, S1PTW = 0
[    1.807183] Data abort info:
[    1.810106]   ISV = 0, ISS = 0x00000004
[    1.813938]   CM = 0, WnR = 0
[    1.816951] [0000000000000040] user address but active_mm is swapper
[    1.823345] Internal error: Oops: 96000004 [#1] PREEMPT SMP
[    1.828900] Modules linked in:
[    1.831948] CPU: 0 PID: 135 Comm: kworker/0:1H Not tainted 5.10.162-g76b3e88d56 #1
[    1.839497] Hardware name: Texas Instruments J721S2 EVM (DT)
[    1.845155] Workqueue: kblockd blk_mq_run_work_fn
[    1.849846] pstate: 20000005 (nzCv daif -PAN -UAO -TCO BTYPE=--)
[    1.855838] pc : __blk_rq_map_sg+0x80/0x500
[    1.860006] lr : __blk_rq_map_sg+0xd4/0x500
[    1.864174] sp : ffff8000128e39e0
[    1.867476] x29: ffff8000128e39e0 x28: ffff000865947000 
[    1.872773] x27: 0000000000000000 x26: ffff8000128e3ab0 
[    1.878070] x25: 0000000000000002 x24: ffff0008659f1000 
[    1.883367] x23: ffff00086592cd00 x22: 000000000000f30a 
[    1.888664] x21: 0000000000000004 x20: ffff00086518bdc0 
[    1.893961] x19: 0000000000001000 x18: 0000000000000010 
[    1.899258] x17: 0000000000000000 x16: fffffe00209033c8 
[    1.904555] x15: 000003ba85e687d5 x14: 00000000ffffffff 
[    1.909852] x13: 00000008ffffffff x12: 0000000000000001 
[    1.915149] x11: fffffe0021767bc0 x10: 000000000000f000 
[    1.920446] x9 : 0000000000000004 x8 : ffff00086592cf80 
[    1.925742] x7 : 0000000000000001 x6 : 0000000000000000 
[    1.931039] x5 : 0000000000000200 x4 : 0000000000000000 
[    1.936336] x3 : ffff8000128e3ab0 x2 : 0000000000000040 
[    1.941633] x1 : fffffe0021767bc0 x0 : 0000000000000040 
[    1.946931] Call trace:
[    1.949367]  __blk_rq_map_sg+0x80/0x500
[    1.953192]  mmc_queue_map_sg+0x3c/0x60
[    1.957015]  mmc_blk_data_prep+0x1a8/0x340
[    1.961097]  mmc_blk_mq_issue_rq+0x478/0x8a0
[    1.965353]  mmc_mq_queue_rq+0x118/0x2b0
[    1.969262]  blk_mq_dispatch_rq_list+0x104/0x778
[    1.973864]  __blk_mq_sched_dispatch_requests+0xd4/0x1a0
[    1.979161]  blk_mq_sched_dispatch_requests+0x38/0x78
[    1.984196]  __blk_mq_run_hw_queue+0xac/0x128
[    1.988538]  blk_mq_run_work_fn+0x20/0x30
[    1.992538]  process_one_work+0x1a0/0x328
[    1.996534]  worker_thread+0x4c/0x420
[    2.000184]  kthread+0x140/0x160
[    2.003400]  ret_from_fork+0x10/0x34
[    2.006966] Code: f9403704 d37c7ea0 2a1503e9 8b000082 (f860688b) 
[    2.013046] ---[ end trace aa4c7ecd0abebdb6 ]---
[    2.017648] Kernel panic - not syncing: Oops: Fatal exception
[    2.023376] SMP: stopping secondary CPUs
[    2.027291] Kernel Offset: 0x80000 from 0xffff800010000000
[    2.032758] PHYS_OFFSET: 0x80000000
[    2.036234] CPU features: 0x28040022,20806008
[    2.040576] Memory Limit: none
[    2.043622] Rebooting in 1 seconds..

Our SBL uses the EMMC UDA startup mode

It is worth mentioning that in the SD card startup mode, the startup will be very smooth,
However, in the case of EMMC startup, the above error will be encountered

Do you have any suggestions?

Thank you in advance for your help

over 2 years ago

0 Parth Nagpal over 2 years ago

TI__Mastermind 42135 points

Hi,

Are you also following the same procedure as mentioned in the thread you linked?

Regards,
Parth

0 li liu over 2 years ago in reply to Parth Nagpal

Intellectual 530 points

Hello Parth

Thank you for your reply

I have identified the problem, but there is no solution
Since the default code only supports loading SBL for SD cards, so I attempted to add SBL loading for emmc in bootapp

This is the code I modified for the SBL startup of EMMC

boot_app_main.c：

/*
*
* Copyright (c) 2022 Texas Instruments Incorporated
*
* All rights reserved not granted herein.
*
* Limited License.
*
* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
* license under copyrights and patents it now or hereafter owns or controls to make,
* have made, use, import, offer to sell and sell ("Utilize") this software subject to the
* terms herein.  With respect to the foregoing patent license, such license is granted
* solely to the extent that any such patent is necessary to Utilize the software alone.
* The patent license shall not apply to any combinations which include this software,
* other than combinations with devices manufactured by or for TI ("TI Devices").
* No hardware patent is licensed hereunder.
*
* Redistributions must preserve existing copyright notices and reproduce this license
* (including the above copyright notice and the disclaimer and (if applicable) source
* code license limitations below) in the documentation and/or other materials provided
* with the distribution
*
* Redistribution and use in binary form, without modification, are permitted provided
* that the following conditions are met:
*
* *       No reverse engineering, decompilation, or disassembly of this software is
* permitted with respect to any software provided in binary form.
*
* *       any redistribution and use are licensed by TI for use only with TI Devices.
*
* *       Nothing shall obligate TI to provide you with source code for the software
* licensed and provided to you in object code.
*
* If software source code is provided to you, modification and redistribution of the
* source code are permitted provided that the following conditions are met:
*
* *       any redistribution and use of the source code, including any resulting derivative
* works, are licensed by TI for use only with TI Devices.
*
* *       any redistribution and use of any object code compiled from the source code
* and any resulting derivative works, are licensed by TI for use only with TI Devices.
*
* Neither the name of Texas Instruments Incorporated nor the names of its suppliers
*
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* DISCLAIMER.
*
* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

/**
 *  \file boot_app_main.c
 *
 *  \brief Main file for building boot app build
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include "boot_app_priv.h"

#if (defined (BUILD_MCU1_0) && (defined (SOC_J721E) || defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4)))
#include <ti/drv/sciclient/sciserver_tirtos.h>
#endif

#if defined(BOOT_MMCSD) ||  defined(BOOT_EMMC) 
#include "boot_app_mmcsd.h"
#elif defined(BOOT_OSPI)
#include "boot_app_ospi.h"
#endif

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

/* Test application stack size */
#define APP_TASK_STACK                  (10U * 1024U)
/**< Task Priority Levels */
#define BOOT_TASK_PRIORITY              (2)

/* uncomment the following for debug logs */
// #define UART_PRINT_DEBUG

/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */

/* None */

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
static void BootApp_TaskFxn(void* a0, void* a1);
static uint32_t Boot_App();
static void BootApp_AppSetup();
static int32_t BootApp_RequestStageCores(uint8_t stageNum);
static int32_t BootApp_ReleaseStageCores(uint8_t stageNum);
static void BootApp_ArmR5PmuCntrInit();
static uint32_t BootApp_GetTimeInMicroSec(uint32_t pmuCntrVal);
static uint32_t BootApp_SetupSciServer(void);

/* Function Pointer used while reading data from the storage. */
extern int32_t   (*fp_readData)(void *dstAddr, void *srcAddr, uint32_t length);
extern void     (*fp_seek)(void *srcAddr, uint32_t location);

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/* Stack for the Boot task */
static uint8_t gBootAppTaskStack[APP_TASK_STACK] __attribute__((aligned(32)));
TaskP_Handle gbootTask;
static uint64_t gtimeBootAppStart, gtimeBootAppFinish;

int32_t main(void)
{
    Board_initCfg boardCfg;
    uint32_t ret = CSL_PASS;
    TaskP_Params bootTaskParams;
    
    boardCfg = BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_UART_STDIO;
    Board_init(boardCfg);
    OS_init();
    
    ret = BootApp_SetupSciServer();
    if(ret != CSL_PASS)
    {
        UART_printf("\nFailed to setup sciserver for boot app\r\n");
        OS_stop();
    }

    BootApp_ArmR5PmuCntrInit();

    UART_printf("\nMCU R5F App started at %d usecs\r\n", BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM)));

    /* Initialize the task params */
    TaskP_Params_init(&bootTaskParams);
    bootTaskParams.priority       = BOOT_TASK_PRIORITY;
    bootTaskParams.stack          = gBootAppTaskStack;
    bootTaskParams.stacksize      = sizeof (gBootAppTaskStack);

    gbootTask = TaskP_create(&BootApp_TaskFxn, &bootTaskParams);
    if (NULL == gbootTask)
    {
        UART_printf("\nBoot Task creation failed\r\n");
        OS_stop();
    }

    OS_start();    /* does not return */

    return(0);
}

static void BootApp_TaskFxn(void* a0, void* a1)
{
    gtimeBootAppStart = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM));

    Boot_App();

    gtimeBootAppFinish = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM));

    UART_printf("\nMCU Boot Task started at %d usecs and finished at %d usecs\r\n", (uint32_t)gtimeBootAppStart, (uint32_t)gtimeBootAppFinish);

    return;
}

uint32_t Boot_App()
{
    uint32_t       retVal;
    cpu_core_id_t  core_id;
    cpu_core_id_t  booted_core_ids[DSP2_C7X_ID];
    uint8_t        i, j;
    cpu_core_id_t *boot_array;
    uint8_t        num_cores_to_boot;
    uint8_t        num_booted_cores = 0;
    uint64_t       time_boot_core_finish[DSP2_C7X_ID];

#if defined(BOOT_OSPI)
    SBL_SPI_init();
    SBL_ospiInit(&boardHandle);
#endif

    /* Configuration of items needed by apps on some cores, before they boot */
    BootApp_AppSetup();

#if defined(BOOT_MMCSD) ||  defined(BOOT_EMMC) 

    retVal = BootApp_MMCBootImageInit();
    if (retVal != CSL_PASS)
    {
        UART_printf("Failure during BootApp_MMCBootImageInit\n\n");
    }
#endif

    /* Initialize the entry point array to 0. */
    for (core_id = MPU1_CPU0_ID; core_id < NUM_CORES; core_id ++)
        (&gK3xx_evmEntry)->CpuEntryPoint[core_id] = SBL_INVALID_ENTRY_ADDR;

    for (j = 0; j < NUM_BOOT_STAGES; j++)
    {

        retVal = BootApp_RequestStageCores(j);

        if (retVal != CSL_PASS)
        {
            UART_printf("Failed to request all late cores in Stage %d\n\n", j);
            BootApp_ReleaseStageCores(j);
        } else
        {
            UART_printf("Loading BootImage\n");

            #if defined(BOOT_MMCSD) ||  defined(BOOT_EMMC) 
                retVal = BootApp_MMCSDBootStageImage(&gK3xx_evmEntry, mmcsd_main_domain_rtos_image_name[j]);
            #endif

            #if defined(BOOT_OSPI)
                retVal = BootApp_OSPIBootStageImage(&gK3xx_evmEntry, ospi_main_domain_flash_rtos_images[j]);
            #endif

            UART_printf("BootImage completed, status = %d\n", retVal);

            if (retVal != CSL_PASS)
            {
                UART_printf("Failure during image copy and parsing\n\n");
            } 
            else
            {
                retVal = BootApp_ReleaseStageCores(j);
                if (retVal != CSL_PASS)
                {
                    UART_printf("Failed to release all late cores\n\n");
                }
            }
        } /* if (retVal != CSL_PASS) */

        if (retVal == CSL_PASS)
        {
            /* Start the individual cores for the boot stage */
            num_cores_to_boot = num_cores_per_boot_stage[j];
            boot_array        = boot_array_stage[j];
            for (i = 0; i < num_cores_to_boot; i++)
            {
                core_id = boot_array[i];
                /* Try booting all cores other than the cluster running the SBL */
                if ((gK3xx_evmEntry.CpuEntryPoint[core_id] != SBL_INVALID_ENTRY_ADDR) &&
                    ((core_id != MCU1_CPU1_ID) && (core_id != MCU1_CPU0_ID)))
                {
                    SBL_SlaveCoreBoot(core_id, 0, &gK3xx_evmEntry, SBL_REQUEST_CORE);
                    UART_printf("SBL_SlaveCoreBoot completed for Core ID#%d, Entry point is 0x%x\n",
                                    core_id, gK3xx_evmEntry.CpuEntryPoint[core_id]);
                    booted_core_ids[num_booted_cores] = core_id;
                    time_boot_core_finish[num_booted_cores] = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM));
                    num_booted_cores++;
                }
            }
        } /* if (retVal == CSL_PASS) */
    } /* for (j = 0; j < NUM_BOOT_STAGES; j++) */

#if defined(BOOT_MMCSD) ||  defined(BOOT_EMMC) 
    BootApp_MMCBootImageDeInit();
#endif

#if defined(BOOT_OSPI)
    SBL_ospiClose(&boardHandle);

    BootApp_OSPILeaveConfigSPI();
#endif

    /* Delay print out of boot log to avoid prints by other tasks */
    TaskP_sleep(4000);

    if (retVal == CSL_PASS)
    {
        /* Print boot log, including all gathered timestamps */
        UART_printf("Boot App: Started at %d usec\n",
                        (uint32_t)gtimeBootAppStart);

        UART_printf("Boot App: Total Num booted cores = %d\n",
                        num_booted_cores);

        for (core_id = 0; core_id < num_booted_cores; core_id++)
        {
            UART_printf("Boot App: Booted Core ID #%d at %d usecs\n",
                            booted_core_ids[core_id],
                            (uint32_t)time_boot_core_finish[core_id]);
        }
    } /* if (retVal == CSL_PASS) */
    else
    {
        UART_printf("Boot App: Failure occurred in boot sequence\n");
    }

    return (retVal);
}

static int32_t BootApp_RequestStageCores(uint8_t stageNum)
{
    uint32_t i;
    int32_t  status = CSL_EFAIL;
    uint8_t  stage  = stageNum;

    for (i = 0; i < MAX_CORES_PER_STAGE; i++)
    {
        if (sbl_late_slave_core_stages_info[stage][i].tisci_proc_id != SBL_INVALID_ID)
        {
            #if defined(UART_PRINT_DEBUG)
                UART_printf("Calling Sciclient_procBootRequestProcessor, ProcId 0x%x... \n",
                            sbl_late_slave_core_stages_info[stage][i].tisci_proc_id);
            #endif
            status = Sciclient_procBootRequestProcessor(sbl_late_slave_core_stages_info[stage][i].tisci_proc_id,
                                                        SCICLIENT_SERVICE_WAIT_FOREVER);
            if (status != CSL_PASS)
            {
                #if defined(UART_PRINT_DEBUG)
                    UART_printf("Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n",
                                        sbl_late_slave_core_stages_info[stage][i].tisci_proc_id);
                #endif
                break;
            }
        }
    }

    return (status);
}

static int32_t BootApp_ReleaseStageCores(uint8_t stageNum)
{
    uint32_t i;
    int32_t  status   = CSL_EFAIL;
    uint8_t  stage  = stageNum;

    for (i = 0; i < MAX_CORES_PER_STAGE; i++)
    {
        if (sbl_late_slave_core_stages_info[stage][i].tisci_proc_id != SBL_INVALID_ID)
        {
            #if defined(UART_PRINT_DEBUG)
                UART_printf("Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n",
                            sbl_late_slave_core_stages_info[stage][i].tisci_proc_id);
            #endif
            status = Sciclient_procBootReleaseProcessor(sbl_late_slave_core_stages_info[stage][i].tisci_proc_id,
                                                        TISCI_MSG_FLAG_AOP,
                                                        SCICLIENT_SERVICE_WAIT_FOREVER);
            if (status != CSL_PASS)
            {
                UART_printf("Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n",
                            sbl_late_slave_core_stages_info[stage][i].tisci_proc_id);
                break;
            }
        }
    }

    return (status);
}

void BootApp_ArmR5PmuCntrInit()
{
    uint32_t val;
    CSL_armR5PmuCfg(0, 0, 1);
    /* Clear the overflow */
    val = CSL_armR5PmuReadCntrOverflowStatus();
    val &= 0x80000000;
    CSL_armR5PmuClearCntrOverflowStatus(val);
    CSL_armR5PmuCfgCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM, CSL_ARM_R5_PMU_EVENT_TYPE_CYCLE_CNT);
    CSL_armR5PmuEnableAllCntrs(1);
    CSL_armR5PmuEnableCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM, 1);
}

uint32_t BootApp_GetTimeInMicroSec(uint32_t pmuCntrVal){
    uint64_t mcu_clk_freq = SBL_MCU1_CPU0_FREQ_HZ;
    uint32_t cycles_per_usec = (mcu_clk_freq / 1000000);
    return (pmuCntrVal/cycles_per_usec);
}

#if defined(MPU1_HLOS_BOOT_ENABLED)
/* Function to clean the MCU R5 cache for a given start address and given memory size */
void BootApp_McuDCacheClean(void *addr, uint32_t size)
{
    /* Invalidate by MVA */
    CSL_armR5CacheWbInv((const void *)addr, uint32_to_int32(size), (bool)TRUE);
}
#endif

static void BootApp_AppSetup(void)
{
#if defined(SOC_J721E)
    Board_STATUS status;

    /* Ethernet config: set proper board muxes for J712E Eth. firmware */
    /* Set IO Expander to use RMII on GESI board */
    status = Board_control(BOARD_CTRL_CMD_SET_RMII_DATA_MUX, NULL);
    if (status != BOARD_SOK)
    {
        UART_printf("Board_control failed to configure RMII pins\n");
    }
    /* Enable CPSW9G MDIO mux */
    status = Board_control(BOARD_CTRL_CMD_SET_GESI_CPSW_MDIO_MUX, NULL);
    if (status != BOARD_SOK)
    {
        UART_printf("Board_control failed to configure CPSW9G MDIO mux\n");
    }
#endif
}

uint32_t BootApp_SetupSciServer(void)
{
    #if (defined (BUILD_MCU1_0) && (defined (SOC_J721E) || defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4)))
        Sciserver_TirtosCfgPrms_t appPrms;
        Sciclient_ConfigPrms_t clientPrms;
        uint32_t ret = CSL_PASS;

        appPrms.taskPriority[SCISERVER_TASK_USER_LO] = 1;
        appPrms.taskPriority[SCISERVER_TASK_USER_HI] = 4;

        /* Sciclient needs to be initialized before Sciserver. Sciserver depends on
        * Sciclient API to execute message forwarding */
        ret = Sciclient_configPrmsInit(&clientPrms);
        if (ret == CSL_PASS)
        {
            ret = Sciclient_init(&clientPrms);
        }

        if (ret == CSL_PASS)
        {
            ret = Sciserver_tirtosInit(&appPrms);
        }

        if (ret == CSL_PASS)
        {
            UART_printf("Starting Sciserver..... PASSED\n");
        }
        else
        {
            UART_printf("Starting Sciserver..... FAILED\n");
        }

    #endif
    return ret;
}

boot_app_mmcsd.c：

/*
*
* Copyright (c) 2022 Texas Instruments Incorporated
*
* All rights reserved not granted herein.
*
* Limited License.
*
* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
* license under copyrights and patents it now or hereafter owns or controls to make,
* have made, use, import, offer to sell and sell ("Utilize") this software subject to the
* terms herein.  With respect to the foregoing patent license, such license is granted
* solely to the extent that any such patent is necessary to Utilize the software alone.
* The patent license shall not apply to any combinations which include this software,
* other than combinations with devices manufactured by or for TI ("TI Devices").
* No hardware patent is licensed hereunder.
*
* Redistributions must preserve existing copyright notices and reproduce this license
* (including the above copyright notice and the disclaimer and (if applicable) source
* code license limitations below) in the documentation and/or other materials provided
* with the distribution
*
* Redistribution and use in binary form, without modification, are permitted provided
* that the following conditions are met:
*
* *       No reverse engineering, decompilation, or disassembly of this software is
* permitted with respect to any software provided in binary form.
*
* *       any redistribution and use are licensed by TI for use only with TI Devices.
*
* *       Nothing shall obligate TI to provide you with source code for the software
* licensed and provided to you in object code.
*
* If software source code is provided to you, modification and redistribution of the
* source code are permitted provided that the following conditions are met:
*
* *       any redistribution and use of the source code, including any resulting derivative
* works, are licensed by TI for use only with TI Devices.
*
* *       any redistribution and use of any object code compiled from the source code
* and any resulting derivative works, are licensed by TI for use only with TI Devices.
*
* Neither the name of Texas Instruments Incorporated nor the names of its suppliers
*
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* DISCLAIMER.
*
* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

/**
 *  \file boot_app_mmcsd.c
 *
 *  \brief supporting file for main file for mmcsd
 */

#include "boot_app_priv.h"
#include "boot_app_mmcsd.h"

#if defined(BOOT_EMMC)
MMCSD_v2_HwAttrs MMCSDInitCfg_EMMC =
{
    1,
    CSL_MMCSD0_CTL_CFG_BASE,
    CSL_MMCSD0_SS_CFG_BASE , /* SS Registers */
    CSL_MMCSD0_SS_CFG_BASE + 0x100,/* PHY  Registers */
    CSLR_R5FSS0_CORE1_INTR_MMCSD0_EMMCSS_INTR_0, /* Corresponds to MAIN_R5_CORE1
                                                    This will update dynamically either through
                                                    dedicated interrupt line or query from BoardCfg*/
    0,
    200000000U,
    25000000U,
    MMCSD_CARD_EMMC,
    MMCSD_BUS_WIDTH_8BIT,
    (MMCSD_BUS_VOLTAGE_1_8V | MMCSD_BUS_VOLTAGE_3_3V),
    1,
    0,
    NULL, /* ioDelay Fn */
    NULL,
    NULL, // MMCSD_inputClockControl,
    1,  /* Enable DMA by default */
    0, /* edmaChRx */
    0, /* edmaChTx */
    0U,
    0U,
    0U,
    0U,
    0U,
    NULL,
    0, /* Crossbar default for IPU1 */
    0, /* Crossbar mux in */
    0,  /* Cross bar instance number for IRQ66 used in eventNum */
    MMCSD_SUPPORT_MMC_ALL, /* Supported modes */
    MMCSD_configSocIntrPath,
    MMCSD_HW_PHY,
    MMCSD_AUTO_HW_TUNING
};
#endif

int32_t BootApp_MMCBootImageInit()
{
    int32_t retVal = E_PASS;
    MMCSD_v2_HwAttrs hwAttrsConfig;


    if (MMCSD_socGetInitCfg(FATFS_initCfg[0].drvInst,&hwAttrsConfig) != 0)
    {
        UART_printf("\nUnable to get config.Exiting. TEST FAILED.\r\n");
        retVal = E_FAIL;
    }


#if defined(BOOT_EMMC)
    hwAttrsConfig = MMCSDInitCfg_EMMC;
#endif

    hwAttrsConfig.enableInterrupt = ((uint32_t)(0U));
    hwAttrsConfig.configSocIntrPath=NULL;

#if defined(EMMC_DEBUG)
    char str[400];
    sprintf(str ,"\n Aodlee instNum=%d baseAddr=%d ssBaseAddr=%d phyBaseAddr=%d intNum=%d \r\n", \
        hwAttrsConfig.instNum, hwAttrsConfig.baseAddr, hwAttrsConfig.baseAddr, hwAttrsConfig.ssBaseAddr, hwAttrsConfig.phyBaseAddr);
    UART_printf(str);
    sprintf(str, "\n Aodlee eventId=%d inputClk=%d outputClk=%d cardType=%d supportedBusWidth=%d \r\n", \
        hwAttrsConfig.eventId, hwAttrsConfig.inputClk, hwAttrsConfig.outputClk, hwAttrsConfig.cardType, hwAttrsConfig.supportedBusWidth);
    UART_printf(str);
    sprintf(str, "\n Aodlee supportedBusVoltages=%d isHighSpeed=%d enableInterrupt=%d enableDma=%d rxDmaEventNumber=%d \r\n", \
        hwAttrsConfig.supportedBusVoltages, hwAttrsConfig.isHighSpeed, hwAttrsConfig.enableInterrupt, hwAttrsConfig.enableDma, hwAttrsConfig.rxDmaEventNumber);
    UART_printf(str);
    sprintf(str, "\n Aodlee txDmaEventNumber=%d edmaTxTCC=%d edmaRxTCC=%d edmaTxTC=%d edmaRxTC=%d \r\n", \
        hwAttrsConfig.txDmaEventNumber, hwAttrsConfig.edmaTxTCC, hwAttrsConfig.edmaRxTCC, hwAttrsConfig.edmaTxTC, hwAttrsConfig.edmaRxTC);
    UART_printf(str);
    sprintf(str, "\n Aodlee version=%d muxNum=%d muxInEvent=%d muxOutEvent=%d supportedModes=%d \r\n", \
        hwAttrsConfig.version, hwAttrsConfig.muxNum, hwAttrsConfig.muxInEvent, hwAttrsConfig.muxOutEvent, hwAttrsConfig.supportedModes);
    UART_printf(str);
    sprintf(str, "\n Aodlee phyType=%d tuningType=%d \r\n", \
        hwAttrsConfig.phyType, hwAttrsConfig.tuningType);
    UART_printf(str);
#endif

    if (MMCSD_socSetInitCfg(FATFS_initCfg[0].drvInst,&hwAttrsConfig) != 0)
    {
        UART_printf("\nUnable to set config.Exiting. TEST FAILED.\r\n");
        retVal = E_FAIL;
    }

    /* Initialization of the driver. */
    FATFS_init();

    /* MMCSD FATFS initialization */
    FATFS_open(0U, NULL, &sbl_fatfsHandle);

    return (retVal);
}

void BootApp_MMCBootImageDeInit()
{
    FATFS_close(sbl_fatfsHandle);
    sbl_fatfsHandle = NULL;
}

int32_t BootApp_MMCBootImageLate(sblEntryPoint_t *pEntry, TCHAR *fileName)
{
    int32_t  retVal = E_PASS;
    FIL      fp     = {0};
    FRESULT  fresult;

    fresult = f_open(&fp, fileName, ((BYTE)FA_READ));
    if (fresult != FR_OK)
    {
        UART_printf("\n SD Boot - File open fails \n");
        retVal = E_FAIL;
    }
    else
    {
        UART_printf("\n BootApp_MMCBootImageLate: fp 0x 0x%x, fileName is %s\n",
                    (unsigned int)((void *) &fp), fileName);
            fp_readData = &SBL_FileRead;
            fp_seek     = &SBL_FileSeek;

            retVal = SBL_MulticoreImageParse((void *) &fp, 0, pEntry,
                                                SBL_SKIP_BOOT_AFTER_COPY);

        UART_printf("\n Called SBL_MulticoreImageParse, status = %d\n", retVal);

        f_close(&fp);
    }

    return retVal;
}

int32_t BootApp_MMCSDBootStageImage(sblEntryPoint_t *pEntry, TCHAR *fileName)
{
    int32_t status      = E_FAIL;
    #if defined(MPU1_HLOS_BOOT_ENABLED)
        TCHAR  *fileNameAtf = "0:/atf_optee.appimage";
    #ifdef HLOS_BOOT_QNX_OS
        TCHAR  *fileHLOS    = "0:/ifs_qnx.appimage";
    #else
        TCHAR  *fileNameDtb = "0:/tidtb_linux.appimage";
        TCHAR  *fileHLOS    = "0:/tikernelimage_linux.appimage";
    #endif
    #endif

    if ((NULL != fileName) && (NULL != pEntry))
    {
        if (strcmp(fileName, MAIN_DOMAIN_HLOS_NAME) != 0)
        {
            status = BootApp_MMCBootImageLate(&gK3xx_evmEntry, fileName);
        }
        #if defined(MPU1_HLOS_BOOT_ENABLED)
        else
        {
            /* Read & Parse images for MPU1 HLOS boot from other files */
            status = BootApp_MMCBootImageLate(&gK3xx_evmEntry, fileNameAtf);
            if (status != CSL_PASS)
            {
                UART_printf("Error copying and parsing A72 appimage #1 for HLOS boot\n");
            }
            else
            {
                status = BootApp_MMCBootImageLate(&gK3xx_evmEntry, fileHLOS);
                if (status != CSL_PASS)
                {
                    UART_printf("Error copying and parsing A72 appimage #2 for HLOS boot\n");
                }
                #if defined(HLOS_BOOT_LINUX_OS)
                    else
                    {
                        status = BootApp_MMCBootImageLate(&gK3xx_evmEntry, fileNameDtb);
                        if (status != CSL_PASS)
                        {
                            UART_printf("Error copying and parsing A72 appimage #3 for HLOS boot\n");
                        }
                    }
                #endif
            }
            if (status == CSL_PASS)
            {
                /* Set the A72 entry point at the ATF address */
                (&gK3xx_evmEntry)->CpuEntryPoint[MPU1_CPU0_ID] = ATF_START_RAM_ADDR;
                BootApp_McuDCacheClean((void *)0x70000000, 0x20000);
            }
        } /* if (address == MAIN_DOMAIN_HLOS) */
    #endif /* #if defined(MPU1_HLOS_BOOT_ENABLED)*/
    } /* if ((NULL != fileName) && (NULL != pEntry)) */

    return status;
}

The final problem is located on line 164 of boot_app_mmcsd.c
It should be that MCU1_0 initialized emmc in SBL, which caused a conflict with the emmc initialization in the Linux kernel

Do you have any suggestions or solutions

Thank you for your support

B.R.

0 li liu over 2 years ago in reply to li liu

Intellectual 530 points

I think it's necessary to update the configuration of Linux's emmc

main_sdhci0: mmc@4f80000 {

compatible = "ti,j721e-sdhci-8bit";

reg = <0x00 0x04f80000 0x00 0x1000>,

<0x00 0x04f88000 0x00 0x400>;

interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;

clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;

clock-names = "clk_ahb", "clk_xin";

assigned-clocks = <&k3_clks 98 1>;

assigned-clock-parents = <&k3_clks 98 2>;

bus-width = <8>;

mmc-hs400-1_8v;

mmc-ddr-1_8v;

ti,otap-del-sel-legacy = <0x0>;

ti,otap-del-sel-mmc-hs = <0x0>;

ti,otap-del-sel-ddr52 = <0x6>;

ti,otap-del-sel-hs400 = <0x5>;

ti,itap-del-sel-legacy = <0x10>;

ti,itap-del-sel-mmc-hs = <0xa>;

ti,strobe-sel = <0x77>;

ti,clkbuf-sel = <0x7>;

ti,trm-icp = <0x8>;

mmc-hs200-1_8v;

dma-coherent;

};

0 Tony Li over 2 years ago in reply to li liu

TI__Intellectual 2250 points

Hi, li

You may try remove mmc-hs400-1_8v; and ti,otap-del-sel-hs400 = <0x5>; then rebuild the uImage and try it again.

Best Regards

Tony

0 li liu over 2 years ago in reply to Tony Li

Intellectual 530 points

Hello Tony，

This modification will not fix this issue

Also, are you referring to uImage as Linux kernel image or Uboot

I believe this refers to Linux because we are not using UBOOT

B.R.

0 Parth Nagpal over 2 years ago in reply to li liu

TI__Mastermind 42135 points

Hi,

Apologies for delay in response.
I have been able to reproduce this issue on my end. Investigating this further. Will get back with details.

Regards,
Parth

0 Parth Nagpal over 1 year ago in reply to Parth Nagpal

TI__Mastermind 42135 points

Hi,

This feature has been taken up as a requirement and will be available in SDK 10.0

Regards,
Parth

Processors

Processors forum

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