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McBSP as SPI master timing problems

Whenever I transmit a burst of data (aka more than one word, such that the transmit buffers are both filled), I get a missing clock pulse in between words, which causes the data after the first word to be shifted.

Here is my initialization code:

    TIMER_FSET(CTL0,DATOUT,0);                // Set TOUTP0 to low

    // Hold the transmiter and reciever in reset
    MCBSP_FSET(SPCR1,XRST,0);                // Reset the transmitter
    MCBSP_FSET(SPCR1,RRST,0);                // Reset the receiver

    // Configure the rate generator
    MCBSP_FSET(SRGR1,CLKGDV,BAUD_RATE);        // Set the baudrate
    MCBSP_FSET(SRGR1,FSGM,0);                // Set the frame-sync to generate on each data
                                            //  note: this is not actually used, just set to make the device happy

    // Configure the device as an SPI slave
    MCBSP_FSET(PCR1,FSXM,1);                // Set the FSX pin (unused) to be derived from the internal frame sync
    MCBSP_FSET(XCR1,XDATDLY,1);                // Set to a 1-bit delay to line up data with the clock
    MCBSP_FSET(RCR1,RDATDLY,1);                // Set to a 1-bit delay to line up data with the clock
    MCBSP_FSET(PCR1,CLKXP,1);                // Transmit on the rising edge of the clock
    MCBSP_FSET(PCR1,CLKRP,0);                // Receive on the rising edge of the clock

    // Configure world-lengths, phases, etc
    MCBSP_FSET(RCR1,RPHASE,0);                // Set to single phase receiving
    MCBSP_FSET(RCR1,RFRLEN1,3);                // Set the frame length to 128-bit
    MCBSP_FSET(RCR1,RWDLEN1,5);                // Set the word length to 32-bit
    MCBSP_FSET(XCR1,XPHASE,0);                // Set to single phase transmission
    MCBSP_FSET(XCR1,XFRLEN1,3);                // Set the frame length to 128-bit
    MCBSP_FSET(XCR1,XWDLEN1,5);                // Set the word length to 32-bit

    // Bring the sample rate generator out of reset and wait for it to reset
    MCBSP_FSET(SPCR1,GRST,1);                // Bring the clock generator out of reset
    for(i = 0; i < 10000; i++)
        j++;

    // Set as an SPI device
    MCBSP_FSET(PCR1,CLKXM,1);                // Set the clock as an output,
                                            //  note: we do it here to prevent an erroneous clock burst
    MCBSP_FSET(SPCR1,CLKSTP,2);                // Set the clock to only run during data transmission

    // Bring the device out of reset and wait for it to reset
    MCBSP_FSET(SPCR1,XRST,1);                // Bring the transmitter out of reset
    MCBSP_FSET(SPCR1,RRST,1);                // Bring the receiver out of reset
    for(i = 0; i < 10000; i++)
        j++;

 

and here is my transmission code:

    for(i = 0; i < 4; i++)
    {
        while(MCBSP_FGET(SPCR1,XRDY) == 0);
        MCBSP_RSET(DXR1,data[i]);
    }

I've attached an o-scope capture showing this effect. The data transmitted is 0xACF00F35 four times. The slave is sampling on the rising edge of the clock. Of note, the binary sequence at the boundary is 0101 1010, but notice how the missing clock pulse prevents the first bit from being sampled. How do I fix this?