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TDA4VH-Q1: MCU_PLL1 Tolerance

Reynier Bravo
Prodigy 10 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Hello experts,

   Where can I find any information regarding the tolerance of MCU_PLL1 on TDA4VH?  Need to find the max drift over a 2 bit time period for the following configuration:

  • WKUP_HFOSC0_CLKOUT = 19.2 MHz
  • MCU_PLL1_CKOUT=2400MHz
  • MCU_PLL1_HSDIV2_CLKOUT=80MHz
  • Crystal Tolerance: ±50ppm = 0.005%
  • 0
    TI__Mastermind 20360 points

    The PLL will not drift independent of the crystal.

    There is uncertainty on the clock edge from the PLL but it is not a drift behavior. Typically, this type of uncertainty is referred to as jitter. It will typically form a distribution of periods around the targeted period and the PLL is updated so that the cumulative period over many output clocks is very tightly controlled.

    Kevin