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Original question:

PROCESSOR-SDK-AM64X: mcu_plus_sdk_am64x_08_00_00_21: GPMC driver / header files missing

PROCESSOR-SDK-AM64X: GPMC clock can not be set and the read values doesn't make sense

Boshra
Intellectual 418 points
Part Number: PROCESSOR-SDK-AM64X
Other Parts Discussed in Thread: AM6442

Hello, 

I am using AM6442 board, on a no-RTOS, bare-metal system on Windows. 

My final goal is to use GPMC to connect to an external FPGA and use the UDMA for transfers.

Now as the first step, I am trying to configure the registers and clock for GPMC. I did the following steps:

I enabled the clock for GPMC:

 

    SOC_moduleClockEnable(TISCI_DEV_GPMC0, 1);

I set the configuration registers for GPMC. Since no GPMC driver is provided for AM64x, Instead, based on this link I used the low-level GPMC driver from AM65x. So I didn't need to define the addresses and masks for registers. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1031271/processor-sdk-am64x-mcu_plus_sdk_am64x_08_00_00_21-gpmc-driver-header-files-missing 

Then I tried to read and set the clock frequency for GPMC. Based on the TRM there is only two clock source possible for the GPMC FCLK: PLL0_HSDIV3 or PLL2_HSDIV7.

However in tisci_clocks.h 5 sources defined for GPMC:

 

Based on the above explanation, here are my questions:

1. I believe CLKB is the output clk of GPMC (2).  HSDIV3 and HSDIV7 are the inputs to the mux(5 and 6). ICLK (interface clk) is the same as clk_In (3). and FCLK_MUX_IN (4) is the output of the mux.Do you confirm that?

2. I tried to read the frequency of these different clocks and somehow set the frequency of the final FCLK, but the read values don't make sense. Also, it doesn't change the frequencies. Why?

    status = SOC_moduleSetClockFrequency(
            TISCI_DEV_GPMC0,
            TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN,
            10000000
            ); // status is successful but it doesn't change the frequency

    status = SOC_moduleSetClockFrequency(
            TISCI_DEV_GPMC0,
            TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK,
            10000000
            ); // statys is fail.

    status= Sciclient_pmGetModuleClkFreq(TISCI_DEV_GPMC0,
                                         TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN,
                                         &freqHz,
                                         SystemP_WAIT_FOREVER); // reads 250 MHz

    status= Sciclient_pmGetModuleClkFreq(TISCI_DEV_GPMC0,
                                         TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK,
                                         &freqHz,
                                         SystemP_WAIT_FOREVER); // reads 0 Hz

    status= Sciclient_pmGetModuleClkFreq(TISCI_DEV_GPMC0,
                                         TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK,
                                         &freqHz,
                                         SystemP_WAIT_FOREVER); // reads 0 Hz

    status= Sciclient_pmGetModuleClkFreq(TISCI_DEV_GPMC0,
                                         TISCI_DEV_BOARD0_GPMC0_CLK_IN,
                                         &freqHz,
                                         SystemP_WAIT_FOREVER); // reads 0 Hz

    status= Sciclient_pmGetModuleClkFreq(TISCI_DEV_GPMC0,
                                         TISCI_DEV_BOARD0_GPMC0_CLKLB_IN,
                                         &freqHz,
                                         SystemP_WAIT_FOREVER); // reads 100 MHz

3. based on the following clock tree, I checked PLL0 and PLL0_HSDIV3 and they are both enable and their outputs are enabled (they are all containing the default values set by SYSFW). Based on my calculation based on the data dump of the registers(provided in the table). the HSDIV3_CLKOUT should be 133 MHz. But what I see by using the Sciclient_pmGetModuleClkFreq function is 0 Hz. Why? Is this function supposed to work for GPMC on AM64x?

Register name

Address

Value in application

Fields 

 

0x00680000

61801001

 

 

0x00680008

03FF0801

 

 

0x00680010

68EF3491

 

 

0x00680014

D172BC5A

 

PLL0_CTRL

0x00680020

00018011

Bit 0, DAC_EN = 1: Fractional NC DAC is enabled

Bit 1, DSM_EN = 0 :Delta sigma modulator is disabled

Bit 4, CLK_POSTDIV_EN =1 : post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled

Bit 5, CLK_4PH_EN = 0 : 4-phase dividers disabled.

Bit 8, INTL_BYP_EN = 0 :Output clocks are derived from VCO clock.

Bit 15, PLL_EN = 1: PLL is enabled

Bit 16, BYP_ON_LOCKLOSS =1 : switch to ref clock source when PLL losses lock

Bit 31, BYPASS_EN = 0.

PLL0_STAT

0x00680024

00000001

Bit 0, Lock =1 : PLL is locked

PLL0_FREQ_CTRL_0

0x00680030

00000050

Bits [11-0], FB_DIV_INT = 80: divide by 80

PLL0_FREQ_CTRL_1

0x00680034

00000000

Bits [23-0], FB_DIV_FRAC = 0 :

PLL0_DIV_CTRL

0x00680038

01020001

Bits [5-0], REF_DIV= 1 : Divide by 1

Bits[18-16], POST_DIV1 : Divide by 2

Bits[26-24], POST_DIV2 : Divide by 1

PLL0_SS_CTRL

0x00680040

80000000

 

PLL0_SS_SPREAD

0x00680044

00010001

 

PLL0_CAL_CTRL

0x00680060

80070F73

 

PLL0_CAL_STAT

0x00680064

80000F73

 

PLL0_HSDIV_CTRL0

0x00680080

00008003

Bits[6-0], HSDIV : CLKOUT divider value (HSDIV+1) => divide by 4.

Bit 8, SYNC_DIS = 0 : Changes to DIV value synchronized to prevent glitches.  

Bit 15, CLKOUT_EN = 1 : enable

Bit 31, RESET = 0

PLL0_HSDIV_CTRL1

0x00680084

00008009

Bits[6-0], HSDIV : CLKOUT divider value (HSDIV+1) => divide by 10.

Bit 8, SYNC_DIS = 0 : Changes to DIV value synchronized to prevent glitches.  

Bit 15, CLKOUT_EN = 1 : enable

Bit 31, RESET = 0

PLL0_HSDIV_CTRL2

0x00680088

00008018

Bits[6-0], HSDIV : CLKOUT divider value (HSDIV+1) => divide by 25.

Bit 8, SYNC_DIS = 0 : Changes to DIV value synchronized to prevent glitches.  

Bit 15, CLKOUT_EN = 1 : enable

Bit 31, RESET = 0

PLL0_HSDIV_CTRL3

0x0068008C

0000800E

Bits[6-0], HSDIV : CLKOUT divider value (HSDIV+1) => divide by 15.

Bit 8, SYNC_DIS = 0 : Changes to DIV value synchronized to prevent glitches.  

Bit 15, CLKOUT_EN = 1 : enable

Bit 31, RESET = 0

PLL0_HSDIV_CTRL4

0x00680090

00008007

Bits[6-0], HSDIV : CLKOUT divider value (HSDIV+1) => divide by 8.

Bit 8, SYNC_DIS = 0 : Changes to DIV value synchronized to prevent glitches.  

Bit 15, CLKOUT_EN = 1 : enable

Bit 31, RESET = 0

PLL0_HSDIV_CTRL5

0x00680094

00008004

Bits[6-0], HSDIV : CLKOUT divider value (HSDIV+1) => divide by 5.

Bit 8, SYNC_DIS = 0 : Changes to DIV value synchronized to prevent glitches.  

Bit 15, CLKOUT_EN = 1 : enable

Bit 31, RESET = 0

PLL0_HSDIV_CTRL6

0x00680098

00008004

Bits[6-0], HSDIV : CLKOUT divider value (HSDIV+1) => divide by 5.

Bit 8, SYNC_DIS = 0 : Changes to DIV value synchronized to prevent glitches.  

Bit 15, CLKOUT_EN = 1 : enable

Bit 31, RESET = 0

PLL0_HSDIV_CTRL7

0x0068009C

00008004

Bits[6-0], HSDIV : CLKOUT divider value (HSDIV+1) => divide by 5.

Bit 8, SYNC_DIS = 0 : Changes to DIV value synchronized to prevent glitches.  

Bit 15, CLKOUT_EN = 1 : enable

Bit 31, RESET = 0

PLL0_HSDIV_CTRL8

0x006800A0

00008007

Bits[6-0], HSDIV : CLKOUT divider value (HSDIV+1) => divide by 8.

Bit 8, SYNC_DIS = 0 : Changes to DIV value synchronized to prevent glitches.  

Bit 15, CLKOUT_EN = 1 : enable

Bit 31, RESET = 0

PLL0_HSDIV_CTRL9

0x006800A4

00008002

Bits[6-0], HSDIV : CLKOUT divider value (HSDIV+1) => divide by 3.

Bit 8, SYNC_DIS = 0 : Changes to DIV value synchronized to prevent glitches.  

Bit 15, CLKOUT_EN = 1 : enable

Bit 31, RESET = 0

  

  • 0
    TI__Mastermind 46166 points

    Hello Boshra,

    I am looking at your queries, and you can get a reply by today.

    Regards,

    S.Anil.

  • +1
    TI__Mastermind 46166 points

    Hello Boshra,

    Please see my answers below .

    Boshra said:
    I believe CLKB is the output clk of GPMC (2).  HSDIV3 and HSDIV7 are the inputs to the mux(5 and 6). ICLK (interface clk) is the same as clk_In (3). and FCLK_MUX_IN (4) is the output of the mux.Do you confirm that?

    To set the GPMC clock frequency, we need to call the below functions:

    SOC_moduleClockEnable(TISCI_DEV_GPMC0, 1); > Clock Enable

    SOC_moduleSetClockFrequency(TISCI_DEV_GPMC0,TISCI_DEV_GPMC0_FUNC_CLK,133333333);  > Set Clock Frequency

    Clock setting macros are available below. h file.

    Boshra said:
    . I tried to read the frequency of these different clocks and somehow set the frequency of the final FCLK, but the read values don't make sense. Also, it doesn't change the frequencies. Why?

    Can you please confirm whether the clock is enabled or not before setting the frequency of the GPMC?

    By using the below function, you should enable clock for GPMC. If not, enable clock.

    status = SOC_moduleClockEnable(TISCI_DEV_GPMC0, 1);

    I am assuming that the clock is not enabled. So, you are not able to set the frequency.

     

    Boshra said:
    based on the following clock tree, I checked PLL0 and PLL0_HSDIV3 and they are both enable and their outputs are enabled (they are all containing the default values set by SYSFW). Based on my calculation based on the data dump of the registers(provided in the table). the HSDIV3_CLKOUT should be 133 MHz. But what I see by using the Sciclient_pmGetModuleClkFreq function is 0 Hz. Why? Is this function supposed to work for GPMC on AM64x?

     I am suspecting the same thing. I think you have not enabled the clock for GPMC, which is why you are reading 0 Hz.

    Let's try to enable Clock and see if you are still getting zero frequency or not.

    FYI, the GPMC driver should be available in the next 9.0 release(Release date Mostly Aug End ) , and the GPMC driver should be interfaced to Memories and not FPGA.

    I hope this driver can be helpful for your Application .

    Regards,

    S.Anil.

  • 0 in reply to Swargam Anil
    Intellectual 418 points

    Hi,

    Thanks for your quick response. 

    Swargam Anil said:
    status = SOC_moduleClockEnable(TISCI_DEV_GPMC0, 1);

    Yes, I mentioned at the beginning of my ticket that I have enabled the GPMC clock.

    Swargam Anil said:
    SOC_moduleSetClockFrequency(TISCI_DEV_GPMC0,TISCI_DEV_GPMC0_FUNC_CLK,133333333);  > Set Clock Frequency

    Do you mean I am not able to set any other frequency? I assumed when we use this SetClockFrequency, it's supposed to set the parent clocks and the dividers in a way that I can get the output that I want. It's not the case?

    Thanks,

    Boshra

  • 0 in reply to Boshra
    Intellectual 418 points

    Hi, 

    I have a bigger problem now. I tried to change the div value in the HSDIV3 register. And now I'm not able to program my board anymore. I don't know it it is related to the change I made or not.

    It fails when it tries to load the sciclient_ccs_init.release.out in load_dmsc_hsfs.js. I even load the bootloader again using UART. the bootloader works and it shows me all the CPUs have their clocks. I don't know why all of a sudden I'm not able to program it again. Can you please help me?

    By the way, my device is an HS-FS device. Maybe M3 is preventing me from programming... but why?

     

    Thanks, 

    Boshra

  • 0 in reply to Boshra
    Intellectual 418 points

    I also tried to program the application in another way rather than CCS. I used uart boot mode to program both the bootloader and application but it has the same result. it's able to load the bootloader but not the application. It seems something is preventing the application to be loaded. But I don't understand how changing HSDIV3 register can effect that! I am very confused and I don't know what else to do. 

  • 0 in reply to Boshra
    TI__Mastermind 46166 points

    Hello Boshra,

    Boshra said:
    Do you mean I am not able to set any other frequency? I assumed when we use this SetClockFrequency, it's supposed to set the parent clocks and the dividers in a way that I can get the output that I want. It's not the case?

    You can set any frequency; by default, GPMC is configured at 133 MHz, and if you need 100 MHz, then pass the 100 MHz value. Or, whatever frequency you need, you can pass it in the above API, and based on the input value, PLL divisions should be calculated. Actually, you don't need to set Parent clock and other division values, which are typically taken care of by the above API. The same procedure is used for all  Peripherals. 

    Boshra said:

    Yes, I mentioned at the beginning of my ticket that I have enabled the GPMC clock.

    Sorry . I seem to have missed that line.

    Regards,

    S.Anil.

  • 0 in reply to Boshra
    TI__Mastermind 46166 points

    Hello Boshra,

    Typically, PLL settings should not be controlled directly in your Application .

    It has a firewall configuration. So, users can't access them.

    Please try to remove the update of the HSDIV3 Register value in your Application and also try to call the below function to update the GPMC clock frequency.

    SOC_moduleSetClockFrequency(TISCI_DEV_GPMC0,TISCI_DEV_GPMC0_FUNC_CLK,133333333);  > Set the clock frequency.

    Before enabling clock, I hope you have configured all Pin functionality for GPMC pins.

    Regards,

    S.Anil.

  • 0 in reply to Swargam Anil
    Intellectual 418 points

    Thanks, I tried to use it on the other board I had and it worked. So it seems that I was using another clock. instead of TISCI_DEV_GPMC0,TISCI_DEV_GPMC0_FUNC_CLK that you mentioned, I was using TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN which was a closer match to the name of GPMC clock based on TRM. 

    So now I can get the clock I want for my other board.

    But still, my first board doesn't work. I am able to program the bootloader, but it seems I'm not able to program the application. It doesn't give me the right to write into the address on the RAM for the application. I thought maybe there is an integrity check problem. Since it's failing when it tries to load the application, I suspect it fails the integrity check here:

    If  PLL has firewalls then my changes should have not even been affect anything.

    Maybe I was able to change it, and then there was an ECC calculated based on that on the flash, and then when it tries to load the M3 firmware (that is integrated into bootloader/ boardcfg) it doesn’t match with the integrity value written into flash.

    Since I’m able to load the bootloader but not the Application, and since it says that the integrity check fails, and since resetting the board should reset the register to its default value but still the problem exists, I guess there is an ECC problem related to DMSC firmware integrity check that is written to flash.  

    If it’s the case, I hope you have a backdoor to reset that.

    what should I do to reset my board? as I mentioned earlier I have tried these two and both of them failed:

    1. loading the bootloader with UART. then trying to program it with CCS which it fails. 

    2. loading boot and application both with UART. It loads the bootloader, and it fails after trying to load the application.

      

    Thanks, 
    Boshra

  • 0 in reply to Boshra
    TI__Guru 69541 points

    Hello Boshra,

    Boshra said:
    1. loading the bootloader with UART. then trying to program it with CCS which it fails.

    These steps are incompatible. If you intend to use the "load_dmsc_hsfs.js" script, which initializes the board by loading the System Firmware on DMSC core, you need to work in DEVBOOT mode. On the other hand, if you are already booting the bootloader with UART, you do not need to run the "load_dmsc_hsfs.js" script as the bootloader itself initializes the board. If you have booted SBL_NULL, which initializes all the cores, you can directly go ahead and load your applications with CCS.

    Boshra said:
    2. loading boot and application both with UART. It loads the bootloader, and it fails after trying to load the application.

    Please note for HS-FS boards, you need to use the application images with extension .appimage.hs_fs. The error should not come if you use the right image.

    Regards,

    Prashant

  • 0 in reply to Prashant Shivhare
    Intellectual 418 points
    Prashant Shivhare said:
    These steps are incompatible. If you intend to use the "load_dmsc_hsfs.js" script, which initializes the board by loading the System Firmware on DMSC core, you need to work in DEVBOOT mode. On the other hand, if you are already booting the bootloader with UART, you do not need to run the "load_dmsc_hsfs.js" script as the bootloader itself initializes the board. If you have booted SBL_NULL, which initializes all the cores, you can directly go ahead and load your applications with CCS.

    Yes, I know. I used it to do the bootloader first, then in OSPI mode, Also I tried the DEV_BOOT_MODE and CCS. 

    Prashant Shivhare said:
    Please note for HS-FS boards, you need to use the application images with extension .appimage.hs_fs. The error should not come if you use the right image.

    I am only using one core. So I don't need the appimage while using CCS in DEV_Boot. I can just launch the target and program for R5 using .out after connection.  And I had already worked and programmed the board many times and it's not the first time and this is not my problem either. 

    I appreciate it if you could look into my problem! 

    Just to make it clear again, my board is locked ! and I have completely explained everything, how it happened and what happened, and what is my assumption just a little above! I am not able to program the application on my board. I can program the bootloader (not in dev_boot_mode obviously in other modes like UART) but it's not able to program the application and it shows the error that I put just above.

    Thanks, 

    Boshra

  • 0 in reply to Prashant Shivhare
    Intellectual 418 points

    I will make another thread for my problem. 

  • 0 in reply to Boshra
    TI__Mastermind 46166 points

    Hello Boshra,

    I am closing this thread as your GPMC clock is enabled as per your requirement, and this GPMC clock enabled issue is solved.

    I have seen already that you have raised a new thread for a new issue; please see the below thread.

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1253426/tmds64evm-no-longer-able-to-program-my-hs-fs-board-verification-fails-at-load

    Boshra said:

    Thanks, I tried to use it on the other board I had and it worked. So it seems that I was using another clock. instead of TISCI_DEV_GPMC0,TISCI_DEV_GPMC0_FUNC_CLK that you mentioned, I was using TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN which was a closer match to the name of GPMC clock based on TRM. 

    So now I can get the clock I want for my other board.

    Regards,

    S.Anil.